maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/schedule-if.ll

47 lines
2.0 KiB
LLVM
Raw Normal View History

R600: Enable -verify-machineinstrs in some tests. llvm-svn: 191788
2013-10-02 03:32:38 +08:00
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. llvm-svn: 176835
2013-03-12 07:16:30 +08:00
;REQUIRES: asserts
R600: Fix JUMP handling so that MachineInstr verification can occur This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
2013-03-12 02:15:06 +08:00
define void @main() {
main_body:
[opaque pointer type] Add textual IR support for explicit type parameter to gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
2015-03-14 02:20:45 +08:00
%0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
R600: Fix JUMP handling so that MachineInstr verification can occur This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
2013-03-12 02:15:06 +08:00
%1 = extractelement <4 x float> %0, i32 0
%2 = bitcast float %1 to i32
%3 = icmp eq i32 %2, 0
%4 = sext i1 %3 to i32
%5 = bitcast i32 %4 to float
%6 = bitcast float %5 to i32
%7 = icmp ne i32 %6, 0
br i1 %7, label %ENDIF, label %ELSE
ELSE: ; preds = %main_body
[opaque pointer type] Add textual IR support for explicit type parameter to gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
2015-03-14 02:20:45 +08:00
%8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
R600: Fix JUMP handling so that MachineInstr verification can occur This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
2013-03-12 02:15:06 +08:00
%9 = extractelement <4 x float> %8, i32 0
%10 = bitcast float %9 to i32
%11 = icmp eq i32 %10, 1
%12 = sext i1 %11 to i32
%13 = bitcast i32 %12 to float
%14 = bitcast float %13 to i32
%15 = icmp ne i32 %14, 0
br i1 %15, label %IF13, label %ENDIF
ENDIF: ; preds = %IF13, %ELSE, %main_body
%temp.0 = phi float [ 1.000000e+03, %main_body ], [ 1.000000e+00, %IF13 ], [ 0.000000e+00, %ELSE ]
%temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
%temp3.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
%16 = insertelement <4 x float> undef, float %temp.0, i32 0
%17 = insertelement <4 x float> %16, float %temp1.0, i32 1
%18 = insertelement <4 x float> %17, float 0.000000e+00, i32 2
%19 = insertelement <4 x float> %18, float %temp3.0, i32 3
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics llvm-svn: 275619
2016-07-16 05:27:08 +08:00
call void @llvm.r600.store.swizzle(<4 x float> %19, i32 0, i32 0)
R600: Fix JUMP handling so that MachineInstr verification can occur This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
2013-03-12 02:15:06 +08:00
ret void
IF13: ; preds = %ELSE
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%20 = load <4 x float>, <4 x float> addrspace(8)* null
R600: Fix JUMP handling so that MachineInstr verification can occur This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
2013-03-12 02:15:06 +08:00
%21 = extractelement <4 x float> %20, i32 0
%22 = fsub float -0.000000e+00, %21
%23 = fadd float 1.000000e+03, %22
br label %ENDIF
}
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics llvm-svn: 275619
2016-07-16 05:27:08 +08:00
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)