forked from OSchip/llvm-project
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
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; REQUIRES: asserts
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; RUN: llc < %s -debug-only=codegenprepare -o /dev/null 2>&1 | FileCheck %s
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; These are regression tests for
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; https://bugs.llvm.org/show_bug.cgi?id=34106
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; "ARMTargetLowering::isLegalAddressingMode can accept incorrect
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; addressing modes for Thumb1 target"
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;
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; The Thumb1 target addressing modes don't support scaling.
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; It supports: r1 + r2, where r1 and r2 can be the same register.
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-arm-none-eabi"
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; Test case 01: %n is scaled by 4 (size of i32).
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; Expected: GEP cannot be folded into LOAD.
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; CHECK: local addrmode: [Base:%arrayidx]
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define i32 @load01(i32* %p, i32 %n) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %p, i32 %n
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%0 = load i32, i32* %arrayidx, align 4
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ret i32 %0
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}
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; Test case 02: No scale of %n is needed because the size of i8 is 1.
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; Expected: GEP can be folded into LOAD.
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; CHECK: local addrmode: [Base:%p + 1*%n]
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define i8 @load02(i8* %p, i32 %n) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i8, i8* %p, i32 %n
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%0 = load i8, i8* %arrayidx
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ret i8 %0
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}
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; Test case 03: 2*%x can be represented as %x + %x.
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; Expected: GEP can be folded into LOAD.
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; CHECK: local addrmode: [2*%x]
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define i32 @load03(i32 %x) nounwind {
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entry:
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%mul = shl nsw i32 %x, 1
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%0 = inttoptr i32 %mul to i32*
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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