2018-09-19 18:54:22 +08:00
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//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-09-19 18:54:22 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
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namespace {
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class RISCVExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAtomicBinOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, AtomicRMWInst::BinOp,
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bool IsMasked, int Width,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAtomicMinMaxOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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AtomicRMWInst::BinOp, bool IsMasked, int Width,
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MachineBasicBlock::iterator &NextMBBI);
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2018-11-30 04:43:42 +08:00
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bool expandAtomicCmpXchg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, bool IsMasked,
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int Width, MachineBasicBlock::iterator &NextMBBI);
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2019-06-11 20:57:47 +08:00
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bool expandAuipcInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode);
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2019-04-01 22:42:56 +08:00
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bool expandLoadLocalAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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2019-06-11 20:57:47 +08:00
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bool expandLoadAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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2019-06-19 16:40:59 +08:00
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bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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2018-09-19 18:54:22 +08:00
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};
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char RISCVExpandPseudo::ID = 0;
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bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoAtomicLoadNand32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 32,
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NextMBBI);
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2019-01-17 18:04:39 +08:00
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case RISCV::PseudoAtomicLoadNand64:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 64,
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NextMBBI);
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2018-09-19 18:54:22 +08:00
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case RISCV::PseudoMaskedAtomicSwap32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, true, 32,
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NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadAdd32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Add, true, 32, NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadSub32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Sub, true, 32, NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadNand32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, true, 32,
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NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadMax32:
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return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Max, true, 32,
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NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadMin32:
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return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Min, true, 32,
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NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadUMax32:
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return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMax, true, 32,
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NextMBBI);
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case RISCV::PseudoMaskedAtomicLoadUMin32:
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return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMin, true, 32,
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NextMBBI);
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2018-11-30 04:43:42 +08:00
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case RISCV::PseudoCmpXchg32:
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return expandAtomicCmpXchg(MBB, MBBI, false, 32, NextMBBI);
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2019-01-17 18:04:39 +08:00
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case RISCV::PseudoCmpXchg64:
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return expandAtomicCmpXchg(MBB, MBBI, false, 64, NextMBBI);
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2018-11-30 04:43:42 +08:00
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case RISCV::PseudoMaskedCmpXchg32:
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return expandAtomicCmpXchg(MBB, MBBI, true, 32, NextMBBI);
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2019-04-01 22:42:56 +08:00
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case RISCV::PseudoLLA:
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return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
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2019-06-11 20:57:47 +08:00
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case RISCV::PseudoLA:
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return expandLoadAddress(MBB, MBBI, NextMBBI);
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2019-06-19 16:40:59 +08:00
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case RISCV::PseudoLA_TLS_IE:
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return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_GD:
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return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
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2018-09-19 18:54:22 +08:00
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}
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return false;
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}
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static unsigned getLRForRMW32(AtomicOrdering Ordering) {
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switch (Ordering) {
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default:
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llvm_unreachable("Unexpected AtomicOrdering");
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case AtomicOrdering::Monotonic:
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return RISCV::LR_W;
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case AtomicOrdering::Acquire:
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return RISCV::LR_W_AQ;
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case AtomicOrdering::Release:
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return RISCV::LR_W;
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case AtomicOrdering::AcquireRelease:
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return RISCV::LR_W_AQ;
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case AtomicOrdering::SequentiallyConsistent:
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return RISCV::LR_W_AQ_RL;
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}
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}
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static unsigned getSCForRMW32(AtomicOrdering Ordering) {
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switch (Ordering) {
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default:
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llvm_unreachable("Unexpected AtomicOrdering");
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case AtomicOrdering::Monotonic:
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return RISCV::SC_W;
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case AtomicOrdering::Acquire:
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return RISCV::SC_W;
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case AtomicOrdering::Release:
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return RISCV::SC_W_RL;
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case AtomicOrdering::AcquireRelease:
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return RISCV::SC_W_RL;
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case AtomicOrdering::SequentiallyConsistent:
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return RISCV::SC_W_AQ_RL;
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}
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}
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2019-01-17 18:04:39 +08:00
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static unsigned getLRForRMW64(AtomicOrdering Ordering) {
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switch (Ordering) {
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default:
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llvm_unreachable("Unexpected AtomicOrdering");
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case AtomicOrdering::Monotonic:
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return RISCV::LR_D;
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case AtomicOrdering::Acquire:
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return RISCV::LR_D_AQ;
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case AtomicOrdering::Release:
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return RISCV::LR_D;
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case AtomicOrdering::AcquireRelease:
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return RISCV::LR_D_AQ;
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case AtomicOrdering::SequentiallyConsistent:
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return RISCV::LR_D_AQ_RL;
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}
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}
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static unsigned getSCForRMW64(AtomicOrdering Ordering) {
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switch (Ordering) {
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default:
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llvm_unreachable("Unexpected AtomicOrdering");
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case AtomicOrdering::Monotonic:
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return RISCV::SC_D;
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case AtomicOrdering::Acquire:
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return RISCV::SC_D;
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case AtomicOrdering::Release:
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return RISCV::SC_D_RL;
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case AtomicOrdering::AcquireRelease:
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return RISCV::SC_D_RL;
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case AtomicOrdering::SequentiallyConsistent:
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return RISCV::SC_D_AQ_RL;
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}
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}
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static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) {
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if (Width == 32)
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return getLRForRMW32(Ordering);
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if (Width == 64)
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return getLRForRMW64(Ordering);
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llvm_unreachable("Unexpected LR width\n");
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}
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static unsigned getSCForRMW(AtomicOrdering Ordering, int Width) {
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if (Width == 32)
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return getSCForRMW32(Ordering);
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if (Width == 64)
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return getSCForRMW64(Ordering);
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llvm_unreachable("Unexpected SC width\n");
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}
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2018-09-19 18:54:22 +08:00
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static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
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DebugLoc DL, MachineBasicBlock *ThisMBB,
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MachineBasicBlock *LoopMBB,
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MachineBasicBlock *DoneMBB,
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AtomicRMWInst::BinOp BinOp, int Width) {
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[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Depends on D65919
Reviewers: lenary
Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision for full review was: https://reviews.llvm.org/D65962
llvm-svn: 368629
2019-08-13 06:41:02 +08:00
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg = MI.getOperand(1).getReg();
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Register AddrReg = MI.getOperand(2).getReg();
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Register IncrReg = MI.getOperand(3).getReg();
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2018-09-19 18:54:22 +08:00
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AtomicOrdering Ordering =
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static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
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// .loop:
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2019-01-17 18:04:39 +08:00
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// lr.[w|d] dest, (addr)
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2018-09-19 18:54:22 +08:00
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// binop scratch, dest, val
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2019-01-17 18:04:39 +08:00
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// sc.[w|d] scratch, scratch, (addr)
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2018-09-19 18:54:22 +08:00
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// bnez scratch, loop
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2019-01-17 18:04:39 +08:00
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BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
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2018-09-19 18:54:22 +08:00
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.addReg(AddrReg);
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switch (BinOp) {
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default:
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llvm_unreachable("Unexpected AtomicRMW BinOp");
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case AtomicRMWInst::Nand:
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BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
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.addReg(DestReg)
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.addReg(IncrReg);
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BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
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.addReg(ScratchReg)
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.addImm(-1);
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break;
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}
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2019-01-17 18:04:39 +08:00
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BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
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2018-09-19 18:54:22 +08:00
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.addReg(AddrReg)
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.addReg(ScratchReg);
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BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
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.addReg(ScratchReg)
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.addReg(RISCV::X0)
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.addMBB(LoopMBB);
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}
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static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL,
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2019-08-16 22:27:50 +08:00
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MachineBasicBlock *MBB, Register DestReg,
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Register OldValReg, Register NewValReg,
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Register MaskReg, Register ScratchReg) {
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2018-09-19 18:54:22 +08:00
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assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique");
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assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique");
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assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique");
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// We select bits from newval and oldval using:
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// https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
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// r = oldval ^ ((oldval ^ newval) & masktargetdata);
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BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg)
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.addReg(OldValReg)
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.addReg(NewValReg);
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BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg)
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.addReg(ScratchReg)
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.addReg(MaskReg);
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BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg)
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.addReg(OldValReg)
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.addReg(ScratchReg);
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}
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static void doMaskedAtomicBinOpExpansion(
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const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL,
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MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopMBB,
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MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width) {
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2019-01-17 18:04:39 +08:00
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assert(Width == 32 && "Should never need to expand masked 64-bit operations");
|
[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Depends on D65919
Reviewers: lenary
Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision for full review was: https://reviews.llvm.org/D65962
llvm-svn: 368629
2019-08-13 06:41:02 +08:00
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
|
|
|
Register ScratchReg = MI.getOperand(1).getReg();
|
|
|
|
Register AddrReg = MI.getOperand(2).getReg();
|
|
|
|
Register IncrReg = MI.getOperand(3).getReg();
|
|
|
|
Register MaskReg = MI.getOperand(4).getReg();
|
2018-09-19 18:54:22 +08:00
|
|
|
AtomicOrdering Ordering =
|
|
|
|
static_cast<AtomicOrdering>(MI.getOperand(5).getImm());
|
|
|
|
|
|
|
|
// .loop:
|
|
|
|
// lr.w destreg, (alignedaddr)
|
|
|
|
// binop scratch, destreg, incr
|
|
|
|
// xor scratch, destreg, scratch
|
|
|
|
// and scratch, scratch, masktargetdata
|
|
|
|
// xor scratch, destreg, scratch
|
|
|
|
// sc.w scratch, scratch, (alignedaddr)
|
|
|
|
// bnez scratch, loop
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
|
|
|
|
.addReg(AddrReg);
|
|
|
|
switch (BinOp) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected AtomicRMW BinOp");
|
|
|
|
case AtomicRMWInst::Xchg:
|
[RISCV] Use addi rather than add x0
Summary:
The RISC-V backend used to generate `add <reg>, x0, <reg>` in a few
instances. It seems most places no longer generate this sequence.
This is semantically equivalent to `addi <reg>, <reg>, 0`, but the
latter has the advantage of being noted to be the canonical instruction
to be used for moves (which microarchitectures can and should recognise
as such).
The changed testcases use instruction aliases - `mv <reg>, <reg>` is an
alias for `addi <reg>, <reg>, 0`.
Reviewers: luismarques
Reviewed By: luismarques
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70124
2019-11-15 02:42:33 +08:00
|
|
|
BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
|
|
|
|
.addReg(IncrReg)
|
|
|
|
.addImm(0);
|
2018-09-19 18:54:22 +08:00
|
|
|
break;
|
|
|
|
case AtomicRMWInst::Add:
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addReg(IncrReg);
|
|
|
|
break;
|
|
|
|
case AtomicRMWInst::Sub:
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addReg(IncrReg);
|
|
|
|
break;
|
|
|
|
case AtomicRMWInst::Nand:
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addReg(IncrReg);
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addImm(-1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg,
|
|
|
|
ScratchReg);
|
|
|
|
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
|
|
|
|
.addReg(AddrReg)
|
|
|
|
.addReg(ScratchReg);
|
|
|
|
BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(RISCV::X0)
|
|
|
|
.addMBB(LoopMBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RISCVExpandPseudo::expandAtomicBinOp(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
|
|
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
MachineInstr &MI = *MBBI;
|
|
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
|
|
|
|
// Insert new MBBs.
|
|
|
|
MF->insert(++MBB.getIterator(), LoopMBB);
|
|
|
|
MF->insert(++LoopMBB->getIterator(), DoneMBB);
|
|
|
|
|
|
|
|
// Set up successors and transfer remaining instructions to DoneMBB.
|
|
|
|
LoopMBB->addSuccessor(LoopMBB);
|
|
|
|
LoopMBB->addSuccessor(DoneMBB);
|
|
|
|
DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
|
|
|
|
DoneMBB->transferSuccessors(&MBB);
|
|
|
|
MBB.addSuccessor(LoopMBB);
|
|
|
|
|
|
|
|
if (!IsMasked)
|
|
|
|
doAtomicBinOpExpansion(TII, MI, DL, &MBB, LoopMBB, DoneMBB, BinOp, Width);
|
|
|
|
else
|
|
|
|
doMaskedAtomicBinOpExpansion(TII, MI, DL, &MBB, LoopMBB, DoneMBB, BinOp,
|
|
|
|
Width);
|
|
|
|
|
|
|
|
NextMBBI = MBB.end();
|
|
|
|
MI.eraseFromParent();
|
|
|
|
|
|
|
|
LivePhysRegs LiveRegs;
|
|
|
|
computeAndAddLiveIns(LiveRegs, *LoopMBB);
|
|
|
|
computeAndAddLiveIns(LiveRegs, *DoneMBB);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
|
2019-08-16 22:27:50 +08:00
|
|
|
MachineBasicBlock *MBB, Register ValReg,
|
|
|
|
Register ShamtReg) {
|
2018-09-19 18:54:22 +08:00
|
|
|
BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
|
|
|
|
.addReg(ValReg)
|
|
|
|
.addReg(ShamtReg);
|
|
|
|
BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg)
|
|
|
|
.addReg(ValReg)
|
|
|
|
.addReg(ShamtReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RISCVExpandPseudo::expandAtomicMinMaxOp(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
|
|
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
assert(IsMasked == true &&
|
|
|
|
"Should only need to expand masked atomic max/min");
|
2019-01-17 18:04:39 +08:00
|
|
|
assert(Width == 32 && "Should never need to expand masked 64-bit operations");
|
2018-09-19 18:54:22 +08:00
|
|
|
|
|
|
|
MachineInstr &MI = *MBBI;
|
|
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
|
|
|
|
// Insert new MBBs.
|
|
|
|
MF->insert(++MBB.getIterator(), LoopHeadMBB);
|
|
|
|
MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
|
|
|
|
MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
|
|
|
|
MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
|
|
|
|
|
|
|
|
// Set up successors and transfer remaining instructions to DoneMBB.
|
|
|
|
LoopHeadMBB->addSuccessor(LoopIfBodyMBB);
|
|
|
|
LoopHeadMBB->addSuccessor(LoopTailMBB);
|
|
|
|
LoopIfBodyMBB->addSuccessor(LoopTailMBB);
|
|
|
|
LoopTailMBB->addSuccessor(LoopHeadMBB);
|
|
|
|
LoopTailMBB->addSuccessor(DoneMBB);
|
|
|
|
DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
|
|
|
|
DoneMBB->transferSuccessors(&MBB);
|
|
|
|
MBB.addSuccessor(LoopHeadMBB);
|
|
|
|
|
[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Depends on D65919
Reviewers: lenary
Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision for full review was: https://reviews.llvm.org/D65962
llvm-svn: 368629
2019-08-13 06:41:02 +08:00
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
|
|
|
Register Scratch1Reg = MI.getOperand(1).getReg();
|
|
|
|
Register Scratch2Reg = MI.getOperand(2).getReg();
|
|
|
|
Register AddrReg = MI.getOperand(3).getReg();
|
|
|
|
Register IncrReg = MI.getOperand(4).getReg();
|
|
|
|
Register MaskReg = MI.getOperand(5).getReg();
|
2018-09-19 18:54:22 +08:00
|
|
|
bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max;
|
|
|
|
AtomicOrdering Ordering =
|
|
|
|
static_cast<AtomicOrdering>(MI.getOperand(IsSigned ? 7 : 6).getImm());
|
|
|
|
|
|
|
|
//
|
|
|
|
// .loophead:
|
|
|
|
// lr.w destreg, (alignedaddr)
|
|
|
|
// and scratch2, destreg, mask
|
|
|
|
// mv scratch1, destreg
|
|
|
|
// [sext scratch2 if signed min/max]
|
|
|
|
// ifnochangeneeded scratch2, incr, .looptail
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
|
|
|
|
.addReg(AddrReg);
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addReg(MaskReg);
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addImm(0);
|
|
|
|
|
|
|
|
switch (BinOp) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected AtomicRMW BinOp");
|
|
|
|
case AtomicRMWInst::Max: {
|
|
|
|
insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
|
|
|
|
.addReg(Scratch2Reg)
|
|
|
|
.addReg(IncrReg)
|
|
|
|
.addMBB(LoopTailMBB);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case AtomicRMWInst::Min: {
|
|
|
|
insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
|
|
|
|
.addReg(IncrReg)
|
|
|
|
.addReg(Scratch2Reg)
|
|
|
|
.addMBB(LoopTailMBB);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case AtomicRMWInst::UMax:
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
|
|
|
|
.addReg(Scratch2Reg)
|
|
|
|
.addReg(IncrReg)
|
|
|
|
.addMBB(LoopTailMBB);
|
|
|
|
break;
|
|
|
|
case AtomicRMWInst::UMin:
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
|
|
|
|
.addReg(IncrReg)
|
|
|
|
.addReg(Scratch2Reg)
|
|
|
|
.addMBB(LoopTailMBB);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// .loopifbody:
|
|
|
|
// xor scratch1, destreg, incr
|
|
|
|
// and scratch1, scratch1, mask
|
|
|
|
// xor scratch1, destreg, scratch1
|
|
|
|
insertMaskedMerge(TII, DL, LoopIfBodyMBB, Scratch1Reg, DestReg, IncrReg,
|
|
|
|
MaskReg, Scratch1Reg);
|
|
|
|
|
|
|
|
// .looptail:
|
|
|
|
// sc.w scratch1, scratch1, (addr)
|
|
|
|
// bnez scratch1, loop
|
|
|
|
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg)
|
|
|
|
.addReg(AddrReg)
|
|
|
|
.addReg(Scratch1Reg);
|
|
|
|
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
|
|
|
|
.addReg(Scratch1Reg)
|
|
|
|
.addReg(RISCV::X0)
|
|
|
|
.addMBB(LoopHeadMBB);
|
|
|
|
|
|
|
|
NextMBBI = MBB.end();
|
|
|
|
MI.eraseFromParent();
|
|
|
|
|
|
|
|
LivePhysRegs LiveRegs;
|
|
|
|
computeAndAddLiveIns(LiveRegs, *LoopHeadMBB);
|
|
|
|
computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB);
|
|
|
|
computeAndAddLiveIns(LiveRegs, *LoopTailMBB);
|
|
|
|
computeAndAddLiveIns(LiveRegs, *DoneMBB);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-11-30 04:43:42 +08:00
|
|
|
bool RISCVExpandPseudo::expandAtomicCmpXchg(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,
|
|
|
|
int Width, MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
MachineInstr &MI = *MBBI;
|
|
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
|
|
|
|
// Insert new MBBs.
|
|
|
|
MF->insert(++MBB.getIterator(), LoopHeadMBB);
|
|
|
|
MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB);
|
|
|
|
MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
|
|
|
|
|
|
|
|
// Set up successors and transfer remaining instructions to DoneMBB.
|
|
|
|
LoopHeadMBB->addSuccessor(LoopTailMBB);
|
|
|
|
LoopHeadMBB->addSuccessor(DoneMBB);
|
|
|
|
LoopTailMBB->addSuccessor(DoneMBB);
|
|
|
|
LoopTailMBB->addSuccessor(LoopHeadMBB);
|
|
|
|
DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
|
|
|
|
DoneMBB->transferSuccessors(&MBB);
|
|
|
|
MBB.addSuccessor(LoopHeadMBB);
|
|
|
|
|
[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Depends on D65919
Reviewers: lenary
Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision for full review was: https://reviews.llvm.org/D65962
llvm-svn: 368629
2019-08-13 06:41:02 +08:00
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
|
|
|
Register ScratchReg = MI.getOperand(1).getReg();
|
|
|
|
Register AddrReg = MI.getOperand(2).getReg();
|
|
|
|
Register CmpValReg = MI.getOperand(3).getReg();
|
|
|
|
Register NewValReg = MI.getOperand(4).getReg();
|
2018-11-30 04:43:42 +08:00
|
|
|
AtomicOrdering Ordering =
|
|
|
|
static_cast<AtomicOrdering>(MI.getOperand(IsMasked ? 6 : 5).getImm());
|
|
|
|
|
|
|
|
if (!IsMasked) {
|
|
|
|
// .loophead:
|
2019-01-17 18:04:39 +08:00
|
|
|
// lr.[w|d] dest, (addr)
|
2018-11-30 04:43:42 +08:00
|
|
|
// bne dest, cmpval, done
|
2019-01-17 18:04:39 +08:00
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
|
2018-11-30 04:43:42 +08:00
|
|
|
.addReg(AddrReg);
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addReg(CmpValReg)
|
|
|
|
.addMBB(DoneMBB);
|
|
|
|
// .looptail:
|
2019-01-17 18:04:39 +08:00
|
|
|
// sc.[w|d] scratch, newval, (addr)
|
2018-11-30 04:43:42 +08:00
|
|
|
// bnez scratch, loophead
|
2019-01-17 18:04:39 +08:00
|
|
|
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
|
2018-11-30 04:43:42 +08:00
|
|
|
.addReg(AddrReg)
|
|
|
|
.addReg(NewValReg);
|
|
|
|
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(RISCV::X0)
|
|
|
|
.addMBB(LoopHeadMBB);
|
|
|
|
} else {
|
|
|
|
// .loophead:
|
|
|
|
// lr.w dest, (addr)
|
|
|
|
// and scratch, dest, mask
|
|
|
|
// bne scratch, cmpval, done
|
[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Depends on D65919
Reviewers: lenary
Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision for full review was: https://reviews.llvm.org/D65962
llvm-svn: 368629
2019-08-13 06:41:02 +08:00
|
|
|
Register MaskReg = MI.getOperand(5).getReg();
|
2019-01-17 18:04:39 +08:00
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
|
2018-11-30 04:43:42 +08:00
|
|
|
.addReg(AddrReg);
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addReg(MaskReg);
|
|
|
|
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(CmpValReg)
|
|
|
|
.addMBB(DoneMBB);
|
|
|
|
|
|
|
|
// .looptail:
|
|
|
|
// xor scratch, dest, newval
|
|
|
|
// and scratch, scratch, mask
|
|
|
|
// xor scratch, dest, scratch
|
|
|
|
// sc.w scratch, scratch, (adrr)
|
|
|
|
// bnez scratch, loophead
|
|
|
|
insertMaskedMerge(TII, DL, LoopTailMBB, ScratchReg, DestReg, NewValReg,
|
|
|
|
MaskReg, ScratchReg);
|
2019-01-17 18:04:39 +08:00
|
|
|
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
|
2018-11-30 04:43:42 +08:00
|
|
|
.addReg(AddrReg)
|
|
|
|
.addReg(ScratchReg);
|
|
|
|
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(RISCV::X0)
|
|
|
|
.addMBB(LoopHeadMBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
NextMBBI = MBB.end();
|
|
|
|
MI.eraseFromParent();
|
|
|
|
|
|
|
|
LivePhysRegs LiveRegs;
|
|
|
|
computeAndAddLiveIns(LiveRegs, *LoopHeadMBB);
|
|
|
|
computeAndAddLiveIns(LiveRegs, *LoopTailMBB);
|
|
|
|
computeAndAddLiveIns(LiveRegs, *DoneMBB);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-06-11 20:57:47 +08:00
|
|
|
bool RISCVExpandPseudo::expandAuipcInstPair(
|
2019-04-01 22:42:56 +08:00
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
2019-06-11 20:57:47 +08:00
|
|
|
MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
|
|
|
|
unsigned SecondOpcode) {
|
2019-04-01 22:42:56 +08:00
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
MachineInstr &MI = *MBBI;
|
|
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
|
[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Depends on D65919
Reviewers: lenary
Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision for full review was: https://reviews.llvm.org/D65962
llvm-svn: 368629
2019-08-13 06:41:02 +08:00
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
2019-04-01 22:42:56 +08:00
|
|
|
const MachineOperand &Symbol = MI.getOperand(1);
|
|
|
|
|
|
|
|
MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
|
|
|
|
|
|
|
|
// Tell AsmPrinter that we unconditionally want the symbol of this label to be
|
|
|
|
// emitted.
|
|
|
|
NewMBB->setLabelMustBeEmitted();
|
|
|
|
|
|
|
|
MF->insert(++MBB.getIterator(), NewMBB);
|
|
|
|
|
|
|
|
BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
|
2019-06-11 20:57:47 +08:00
|
|
|
.addDisp(Symbol, 0, FlagsHi);
|
|
|
|
BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
|
2019-04-01 22:42:56 +08:00
|
|
|
.addReg(DestReg)
|
|
|
|
.addMBB(NewMBB, RISCVII::MO_PCREL_LO);
|
|
|
|
|
|
|
|
// Move all the rest of the instructions to NewMBB.
|
|
|
|
NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end());
|
|
|
|
// Update machine-CFG edges.
|
|
|
|
NewMBB->transferSuccessorsAndUpdatePHIs(&MBB);
|
|
|
|
// Make the original basic block fall-through to the new.
|
|
|
|
MBB.addSuccessor(NewMBB);
|
|
|
|
|
|
|
|
// Make sure live-ins are correctly attached to this new basic block.
|
|
|
|
LivePhysRegs LiveRegs;
|
|
|
|
computeAndAddLiveIns(LiveRegs, *NewMBB);
|
|
|
|
|
|
|
|
NextMBBI = MBB.end();
|
|
|
|
MI.eraseFromParent();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-06-11 20:57:47 +08:00
|
|
|
bool RISCVExpandPseudo::expandLoadLocalAddress(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
|
|
|
|
RISCV::ADDI);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RISCVExpandPseudo::expandLoadAddress(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
|
|
|
|
unsigned SecondOpcode;
|
|
|
|
unsigned FlagsHi;
|
|
|
|
if (MF->getTarget().isPositionIndependent()) {
|
|
|
|
const auto &STI = MF->getSubtarget<RISCVSubtarget>();
|
|
|
|
SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
|
|
|
|
FlagsHi = RISCVII::MO_GOT_HI;
|
|
|
|
} else {
|
|
|
|
SecondOpcode = RISCV::ADDI;
|
|
|
|
FlagsHi = RISCVII::MO_PCREL_HI;
|
|
|
|
}
|
|
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi, SecondOpcode);
|
|
|
|
}
|
|
|
|
|
2019-06-19 16:40:59 +08:00
|
|
|
bool RISCVExpandPseudo::expandLoadTLSIEAddress(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
|
|
|
|
const auto &STI = MF->getSubtarget<RISCVSubtarget>();
|
|
|
|
unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
|
|
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
|
|
|
|
SecondOpcode);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RISCVExpandPseudo::expandLoadTLSGDAddress(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
|
|
|
|
RISCV::ADDI);
|
|
|
|
}
|
|
|
|
|
2018-09-19 18:54:22 +08:00
|
|
|
} // end of anonymous namespace
|
|
|
|
|
|
|
|
INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
|
|
|
|
RISCV_EXPAND_PSEUDO_NAME, false, false)
|
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
|
|
|
|
|
|
|
|
} // end of namespace llvm
|