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llvm-project/llvm/lib/Target/MBlaze/MBlazeTargetMachine.h

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- MBlazeTargetMachine.h - Define TargetMachine for MBlaze -*- C++ -*-===//
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the MBlaze specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
#ifndef MBLAZE_TARGETMACHINE_H
#define MBLAZE_TARGETMACHINE_H
Sort includes for all of the .h files under the 'lib' tree. These were missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
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#include "MBlazeFrameLowering.h"
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
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#include "MBlazeISelLowering.h"
Sort includes for all of the .h files under the 'lib' tree. These were missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
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#include "MBlazeInstrInfo.h"
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
#include "MBlazeIntrinsicInfo.h"
Sort includes for all of the .h files under the 'lib' tree. These were missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
2012-12-04 15:12:27 +08:00
#include "MBlazeSelectionDAGInfo.h"
#include "MBlazeSubtarget.h"
Move TargetData to DataLayout. llvm-svn: 165402
2012-10-09 00:38:25 +08:00
#include "llvm/DataLayout.h"
Sort includes for all of the .h files under the 'lib' tree. These were missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
2012-12-04 15:12:27 +08:00
#include "llvm/MC/MCStreamer.h"
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. llvm-svn: 123170
2011-01-10 20:39:04 +08:00
#include "llvm/Target/TargetFrameLowering.h"
Sort includes for all of the .h files under the 'lib' tree. These were missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
2012-12-04 15:12:27 +08:00
#include "llvm/Target/TargetMachine.h"
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke. llvm-svn: 166248
2012-10-19 07:22:48 +08:00
#include "llvm/Target/TargetTransformImpl.h"
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
namespace llvm {
class formatted_raw_ostream;
class MBlazeTargetMachine : public LLVMTargetMachine {
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. llvm-svn: 123170
2011-01-10 20:39:04 +08:00
MBlazeSubtarget Subtarget;
Move TargetData to DataLayout. llvm-svn: 165402
2012-10-09 00:38:25 +08:00
const DataLayout DL; // Calculates type size & alignment
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. llvm-svn: 123170
2011-01-10 20:39:04 +08:00
MBlazeInstrInfo InstrInfo;
MBlazeFrameLowering FrameLowering;
MBlazeTargetLowering TLInfo;
Implement a bunch more TargetSelectionDAGInfo infrastructure. Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
2010-05-12 01:31:57 +08:00
MBlazeSelectionDAGInfo TSInfo;
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. llvm-svn: 123170
2011-01-10 20:39:04 +08:00
MBlazeIntrinsicInfo IntrinsicInfo;
Add scheduling information for the MBlaze backend. llvm-svn: 129311
2011-04-12 06:31:52 +08:00
InstrItineraryData InstrItins;
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke. llvm-svn: 166248
2012-10-19 07:22:48 +08:00
ScalarTargetTransformImpl STTI;
VectorTargetTransformImpl VTTI;
Add scheduling information for the MBlaze backend. llvm-svn: 129311
2011-04-12 06:31:52 +08:00
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
public:
Introduce MCCodeGenInfo, which keeps information that can affect codegen (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
2011-07-19 14:37:02 +08:00
MBlazeTargetMachine(const Target &T, StringRef TT,
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo. - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
2011-07-20 15:51:56 +08:00
StringRef CPU, StringRef FS,
Move global variables in TargetMachine into new TargetOptions class. As an API change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
2011-12-03 06:16:29 +08:00
const TargetOptions &Options,
Sink codegen optimization level into MCCodeGenInfo along side relocation model and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
2011-11-16 16:38:26 +08:00
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; }
Add scheduling information for the MBlaze backend. llvm-svn: 129311
2011-04-12 06:31:52 +08:00
virtual const InstrItineraryData *getInstrItineraryData() const
{ return &InstrItins; }
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. llvm-svn: 123170
2011-01-10 20:39:04 +08:00
virtual const TargetFrameLowering *getFrameLowering() const
{ return &FrameLowering; }
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
virtual const MBlazeSubtarget *getSubtargetImpl() const
{ return &Subtarget; }
Move TargetData to DataLayout. llvm-svn: 165402
2012-10-09 00:38:25 +08:00
virtual const DataLayout *getDataLayout() const
{ return &DL;}
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
virtual const MBlazeRegisterInfo *getRegisterInfo() const
{ return &InstrInfo.getRegisterInfo(); }
Use const qualifiers with TargetLowering. This eliminates several const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
2010-04-17 23:26:15 +08:00
virtual const MBlazeTargetLowering *getTargetLowering() const
{ return &TLInfo; }
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
Implement a bunch more TargetSelectionDAGInfo infrastructure. Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
2010-05-12 01:31:57 +08:00
virtual const MBlazeSelectionDAGInfo* getSelectionDAGInfo() const
{ return &TSInfo; }
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
const TargetIntrinsicInfo *getIntrinsicInfo() const
{ return &IntrinsicInfo; }
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke. llvm-svn: 166248
2012-10-19 07:22:48 +08:00
virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const
{ return &STTI; }
virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const
{ return &VTTI; }
Recommit 116986 with capitalization typo fixed. llvm-svn: 116993
2010-10-21 11:57:26 +08:00
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
// Pass Pipeline Configuration
TargetPassConfig: confine the MC configuration to TargetMachine. Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
2012-02-04 10:56:59 +08:00
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
Adding the MicroBlaze backend. The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
2010-02-24 03:15:24 +08:00
};
} // End llvm namespace
#endif