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llvm-project/llvm/test/CodeGen/Mips/msa/2rf_tq.ll

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[mips][msa] Summarize tests Adds a comment to the start of each test summarizing the area the test covers. llvm-svn: 189465
2013-08-28 18:02:29 +08:00
; Test the MSA floating-point to fixed-point conversion intrinsics that are
; encoded with the 2RF instruction format.
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. llvm-svn: 191498
2013-09-27 18:08:31 +08:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 llvm-svn: 194806
2013-11-15 19:04:16 +08:00
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_ftq_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
define void @llvm_mips_ftq_h_test() nounwind {
entry:
%0 = load <4 x float>* @llvm_mips_ftq_h_ARG1
%1 = load <4 x float>* @llvm_mips_ftq_h_ARG2
%2 = tail call <8 x i16> @llvm.mips.ftq.h(<4 x float> %0, <4 x float> %1)
store <8 x i16> %2, <8 x i16>* @llvm_mips_ftq_h_RES
ret void
}
declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind
; CHECK: llvm_mips_ftq_h_test:
; CHECK: ld.w
; CHECK: ld.w
; CHECK: ftq.h
; CHECK: st.h
; CHECK: .size llvm_mips_ftq_h_test
;
@llvm_mips_ftq_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
@llvm_mips_ftq_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
@llvm_mips_ftq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_ftq_w_test() nounwind {
entry:
%0 = load <2 x double>* @llvm_mips_ftq_w_ARG1
%1 = load <2 x double>* @llvm_mips_ftq_w_ARG2
%2 = tail call <4 x i32> @llvm.mips.ftq.w(<2 x double> %0, <2 x double> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_ftq_w_RES
ret void
}
declare <4 x i32> @llvm.mips.ftq.w(<2 x double>, <2 x double>) nounwind
; CHECK: llvm_mips_ftq_w_test:
; CHECK: ld.d
; CHECK: ld.d
; CHECK: ftq.w
; CHECK: st.w
; CHECK: .size llvm_mips_ftq_w_test
;