llvm-project/llvm/test/CodeGen/Thumb2/thumb2-clz.ll

; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s

define i32 @f1(i32 %a) {
; CHECK: f1:
; CHECK: clz r
    %tmp = tail call i32 @llvm.ctlz.i32(i32 %a)
    ret i32 %tmp
}

declare i32 @llvm.ctlz.i32(i32) nounwind readnone
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590 2011-07-07 11:55:05 +08:00			`; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 \| FileCheck %s`
Thumb-2 has CLZ. llvm-svn: 74322 2009-06-27 04:47:43 +08:00
			`define i32 @f1(i32 %a) {`
Fix Thumb2 failures by converting them to FileCheck. llvm-svn: 85210 2009-10-27 14:31:02 +08:00			`; CHECK: f1:`
			`; CHECK: clz r`
Thumb-2 has CLZ. llvm-svn: 74322 2009-06-27 04:47:43 +08:00			`%tmp = tail call i32 @llvm.ctlz.i32(i32 %a)`
			`ret i32 %tmp`
			`}`

			`declare i32 @llvm.ctlz.i32(i32) nounwind readnone`