2012-02-18 20:03:15 +08:00
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//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
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2011-12-13 05:14:40 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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2011-12-13 05:14:40 +08:00
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2012-03-18 02:46:09 +08:00
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#include "HexagonRegisterInfo.h"
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2012-02-09 02:25:47 +08:00
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#include "MCTargetDesc/HexagonBaseInfo.h"
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2013-05-02 23:39:30 +08:00
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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2011-12-13 05:14:40 +08:00
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#define GET_INSTRINFO_HEADER
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#include "HexagonGenInstrInfo.inc"
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namespace llvm {
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2014-03-15 17:11:41 +08:00
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struct EVT;
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class HexagonSubtarget;
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2011-12-13 05:14:40 +08:00
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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virtual void anchor();
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const HexagonRegisterInfo RI;
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2011-12-13 05:14:40 +08:00
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public:
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explicit HexagonInstrInfo(HexagonSubtarget &ST);
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/// TargetInstrInfo overrides.
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2011-12-13 05:14:40 +08:00
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///
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/// If the specified machine instruction is a direct
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2011-12-13 05:14:40 +08:00
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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2014-04-29 15:58:16 +08:00
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// If the specified machine instruction is a direct
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2011-12-13 05:14:40 +08:00
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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2014-04-29 15:58:16 +08:00
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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2015-11-24 22:55:26 +08:00
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/// Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with a conditional branch and it falls through to a
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/// successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These operands can be
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/// passed to other TargetInstrInfo methods to create new branches.
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/// 4. If this block ends with a conditional branch followed by an
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/// unconditional branch, it returns the 'true' destination in TBB, the
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/// 'false' destination in FBB, and a list of operands that evaluate the
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/// condition. These operands can be passed to other TargetInstrInfo
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/// methods to create new branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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/// If AllowModify is true, then this routine is allowed to modify the basic
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/// block (e.g. delete instructions after the unconditional branch).
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///
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bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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/// Remove the branching code at the end of the specific MBB.
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/// This is only invoked in cases where AnalyzeBranch returns success. It
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/// returns the number of instructions that were removed.
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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/// Insert branch code into the end of the specified MachineBasicBlock.
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/// The operands to this method are the same as those
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/// returned by AnalyzeBranch. This is only invoked in cases where
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/// AnalyzeBranch returns success. It returns the number of instructions
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/// inserted.
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///
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/// It is also invoked by tail merging to add unconditional branches in
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/// cases where AnalyzeBranch doesn't apply because there was no original
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/// branch to analyze. At least this much must be implemented, else tail
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/// merging needs to be disabled.
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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/// Return true if it's profitable to predicate
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/// instructions with accumulated instruction latency of "NumCycles"
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/// of the specified basic block, where the probability of the instructions
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/// being executed is given by Probability, and Confidence is a measure
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/// of our confidence that it will be properly predicted.
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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BranchProbability Probability) const override;
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/// Second variant of isProfitableToIfCvt. This one
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/// checks for the case where two basic blocks from true and false path
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/// of a if-then-else (diamond) are predicated on mutally exclusive
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/// predicates, where the probability of the true path being taken is given
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/// by Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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BranchProbability Probability) const override;
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/// Return true if it's profitable for if-converter to duplicate instructions
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/// of specified accumulated instruction latencies in the specified MBB to
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/// enable if-conversion.
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/// The probability of the instructions being executed is given by
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/// Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override;
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/// Emit instructions to copy a pair of physical registers.
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///
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/// This function should support copies within any legal register class as
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/// well as any cross-class copies created during instruction selection.
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///
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/// The source and destination registers may overlap, which may require a
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/// careful implementation when multiple copy instructions are required for
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/// large registers. See for example the ARM target.
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2014-04-29 15:58:16 +08:00
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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2015-11-24 22:55:26 +08:00
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/// Store the specified register of the given register class to the specified
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/// stack frame index. The store instruction is to be added to the given
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/// machine basic block before the specified machine instruction. If isKill
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/// is true, the register operand is the last use and must be marked kill.
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2014-04-29 15:58:16 +08:00
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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2015-11-24 22:55:26 +08:00
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/// Load the specified register of the given register class from the specified
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/// stack frame index. The load instruction is to be added to the given
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/// machine basic block before the specified machine instruction.
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2014-04-29 15:58:16 +08:00
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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2015-11-24 22:55:26 +08:00
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/// This function is called for all pseudo instructions
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2015-03-10 06:05:21 +08:00
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/// that remain after register allocation. Many pseudo instructions are
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/// created to help register allocation. This is the place to convert them
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/// into real instructions. The target can edit MI in place, or it can insert
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/// new instructions and erase MI. The function should return true if
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/// anything was changed.
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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2015-11-24 22:55:26 +08:00
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/// Reverses the branch condition of the specified condition list,
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/// returning false on success and true if it cannot be reversed.
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const override;
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2015-11-24 22:55:26 +08:00
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/// Insert a noop into the instruction stream at the specified point.
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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2015-11-24 22:55:26 +08:00
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/// Returns true if the instruction is already predicated.
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bool isPredicated(const MachineInstr *MI) const override;
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2015-11-24 22:55:26 +08:00
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/// Convert the instruction into a predicated instruction.
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/// It returns true if the operation was successful.
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bool PredicateInstruction(MachineInstr *MI,
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ArrayRef<MachineOperand> Cond) const override;
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2014-04-29 15:58:16 +08:00
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2015-11-24 22:55:26 +08:00
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/// Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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2015-11-24 22:55:26 +08:00
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/// If the specified instruction defines any predicate
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/// or condition code register(s) used for predication, returns true as well
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/// as the definition predicate(s) by reference.
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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2015-11-24 22:55:26 +08:00
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/// Return true if the specified instruction can be predicated.
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/// By default, this returns true for every instruction with a
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/// PredicateOperand.
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bool isPredicable(MachineInstr *MI) const override;
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2015-11-24 22:55:26 +08:00
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/// Test if the given instruction should be considered a scheduling boundary.
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/// This primarily includes labels and terminators.
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bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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2014-04-29 15:58:16 +08:00
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2015-11-24 22:55:26 +08:00
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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unsigned getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const override;
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/// Allocate and return a hazard recognizer to use for this target when
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/// scheduling the machine instructions after register allocation.
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ScheduleHazardRecognizer*
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
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const ScheduleDAG *DAG) const override;
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/// For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const override;
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/// Compute the instruction latency of a given instruction.
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/// If the instruction has higher cost when predicated, it's returned via
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/// PredCost.
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const override;
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/// Create machine specific model for scheduling.
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DFAPacketizer *
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CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
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2012-02-02 06:13:57 +08:00
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2015-11-24 22:55:26 +08:00
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// Sometimes, it is possible for the target
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// to tell, even without aliasing information, that two MIs access different
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// memory addresses. This function returns true if two MIs access different
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// memory addresses and false otherwise.
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bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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AliasAnalysis *AA = nullptr)
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const override;
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/// HexagonInstrInfo specifics.
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///
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const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
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unsigned createVR(MachineFunction* MF, MVT VT) const;
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bool isAbsoluteSet(const MachineInstr* MI) const;
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bool isAccumulator(const MachineInstr *MI) const;
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bool isComplex(const MachineInstr *MI) const;
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bool isCompoundBranchInstr(const MachineInstr *MI) const;
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bool isCondInst(const MachineInstr *MI) const;
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2012-04-24 02:25:57 +08:00
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bool isConditionalALU32 (const MachineInstr* MI) const;
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2015-11-24 22:55:26 +08:00
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bool isConditionalLoad(const MachineInstr* MI) const;
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2012-05-04 05:52:53 +08:00
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bool isConditionalStore(const MachineInstr* MI) const;
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2015-11-24 22:55:26 +08:00
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bool isConditionalTransfer(const MachineInstr* MI) const;
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bool isConstExtended(const MachineInstr *MI) const;
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2011-12-13 05:14:40 +08:00
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bool isDeallocRet(const MachineInstr *MI) const;
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2015-11-24 22:55:26 +08:00
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bool isDependent(const MachineInstr *ProdMI,
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const MachineInstr *ConsMI) const;
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bool isDotCurInst(const MachineInstr* MI) const;
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bool isDotNewInst(const MachineInstr* MI) const;
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bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
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2015-12-15 05:32:25 +08:00
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bool isEarlySourceInstr(const MachineInstr *MI) const;
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2015-11-24 22:55:26 +08:00
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bool isEndLoopN(unsigned Opcode) const;
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bool isExpr(unsigned OpType) const;
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2012-05-04 05:52:53 +08:00
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bool isExtendable(const MachineInstr* MI) const;
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bool isExtended(const MachineInstr* MI) const;
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2015-12-15 05:32:25 +08:00
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bool isFloat(const MachineInstr *MI) const;
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2015-12-17 03:36:12 +08:00
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bool isHVXMemWithAIndirect(const MachineInstr *I,
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const MachineInstr *J) const;
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2015-11-24 22:55:26 +08:00
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bool isIndirectCall(const MachineInstr *MI) const;
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bool isIndirectL4Return(const MachineInstr *MI) const;
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bool isJumpR(const MachineInstr *MI) const;
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bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
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2015-12-15 05:32:25 +08:00
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bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
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const MachineInstr *ESMI) const;
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bool isLateResultInstr(const MachineInstr *MI) const;
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2015-11-24 22:55:26 +08:00
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bool isLateSourceInstr(const MachineInstr *MI) const;
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2015-12-15 05:32:25 +08:00
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bool isLoopN(const MachineInstr *MI) const;
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2015-11-24 22:55:26 +08:00
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bool isMemOp(const MachineInstr *MI) const;
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bool isNewValue(const MachineInstr* MI) const;
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bool isNewValue(unsigned Opcode) const;
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bool isNewValueInst(const MachineInstr* MI) const;
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bool isNewValueJump(const MachineInstr* MI) const;
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bool isNewValueJump(unsigned Opcode) const;
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2012-05-04 05:52:53 +08:00
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bool isNewValueStore(const MachineInstr* MI) const;
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2013-05-11 04:27:34 +08:00
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bool isNewValueStore(unsigned Opcode) const;
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2015-11-24 22:55:26 +08:00
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bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
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bool isPostIncrement(const MachineInstr* MI) const;
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bool isPredicatedNew(const MachineInstr *MI) const;
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bool isPredicatedNew(unsigned Opcode) const;
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bool isPredicatedTrue(const MachineInstr *MI) const;
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bool isPredicatedTrue(unsigned Opcode) const;
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bool isPredicated(unsigned Opcode) const;
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bool isPredicateLate(unsigned Opcode) const;
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bool isPredictedTaken(unsigned Opcode) const;
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bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
|
2016-02-13 02:37:23 +08:00
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bool isSignExtendingLoad(const MachineInstr *MI) const;
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2015-11-24 22:55:26 +08:00
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bool isSolo(const MachineInstr* MI) const;
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bool isSpillPredRegOp(const MachineInstr *MI) const;
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bool isTC1(const MachineInstr *MI) const;
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bool isTC2(const MachineInstr *MI) const;
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bool isTC2Early(const MachineInstr *MI) const;
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bool isTC4x(const MachineInstr *MI) const;
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bool isV60VectorInstruction(const MachineInstr *MI) const;
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bool isValidAutoIncImm(const EVT VT, const int Offset) const;
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bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
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bool isVecAcc(const MachineInstr *MI) const;
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bool isVecALU(const MachineInstr *MI) const;
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bool isVecUsableNextPacket(const MachineInstr *ProdMI,
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const MachineInstr *ConsMI) const;
|
2016-02-13 02:37:23 +08:00
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bool isZeroExtendingLoad(const MachineInstr *MI) const;
|
2011-12-13 05:14:40 +08:00
|
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|
2013-03-02 01:37:13 +08:00
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|
2015-12-17 03:36:12 +08:00
|
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bool canExecuteInBundle(const MachineInstr *First,
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const MachineInstr *Second) const;
|
2015-11-24 22:55:26 +08:00
|
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|
bool hasEHLabel(const MachineBasicBlock *B) const;
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bool hasNonExtEquivalent(const MachineInstr *MI) const;
|
2015-12-15 05:32:25 +08:00
|
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|
bool hasPseudoInstrPair(const MachineInstr *MI) const;
|
2015-11-24 22:55:26 +08:00
|
|
|
bool hasUncondBranch(const MachineBasicBlock *B) const;
|
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|
|
bool mayBeCurLoad(const MachineInstr* MI) const;
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bool mayBeNewStore(const MachineInstr* MI) const;
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|
|
bool producesStall(const MachineInstr *ProdMI,
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|
const MachineInstr *ConsMI) const;
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|
|
bool producesStall(const MachineInstr *MI,
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|
|
MachineBasicBlock::const_instr_iterator MII) const;
|
2015-12-15 05:32:25 +08:00
|
|
|
bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
|
2015-11-24 22:55:26 +08:00
|
|
|
bool PredOpcodeHasJMP_c(unsigned Opcode) const;
|
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|
|
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
|
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|
|
unsigned getAddrMode(const MachineInstr* MI) const;
|
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|
|
unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
|
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|
|
unsigned &AccessSize) const;
|
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|
|
bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
|
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|
|
unsigned &OffsetPos) const;
|
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|
|
|
SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
|
|
|
|
|
unsigned getCExtOpNum(const MachineInstr *MI) const;
|
|
|
|
|
HexagonII::CompoundGroup
|
|
|
|
|
getCompoundCandidateGroup(const MachineInstr *MI) const;
|
|
|
|
|
unsigned getCompoundOpcode(const MachineInstr *GA,
|
|
|
|
|
const MachineInstr *GB) const;
|
|
|
|
|
int getCondOpcode(int Opc, bool sense) const;
|
|
|
|
|
int getDotCurOp(const MachineInstr* MI) const;
|
|
|
|
|
int getDotNewOp(const MachineInstr* MI) const;
|
2015-12-15 05:32:25 +08:00
|
|
|
int getDotNewPredJumpOp(const MachineInstr *MI,
|
2015-11-24 22:55:26 +08:00
|
|
|
const MachineBranchProbabilityInfo *MBPI) const;
|
2015-12-15 05:32:25 +08:00
|
|
|
int getDotNewPredOp(const MachineInstr *MI,
|
2013-05-02 23:39:30 +08:00
|
|
|
const MachineBranchProbabilityInfo *MBPI) const;
|
2015-11-24 22:55:26 +08:00
|
|
|
int getDotOldOp(const int opc) const;
|
|
|
|
|
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
|
|
|
|
|
const;
|
2015-12-15 05:32:25 +08:00
|
|
|
short getEquivalentHWInstr(const MachineInstr *MI) const;
|
2015-11-24 22:55:26 +08:00
|
|
|
MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
|
|
|
|
|
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
|
|
|
|
|
const MachineInstr *MI) const;
|
|
|
|
|
bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
|
|
|
|
|
unsigned getInvertedPredicatedOpcode(const int Opc) const;
|
2013-03-02 01:37:13 +08:00
|
|
|
int getMaxValue(const MachineInstr *MI) const;
|
2015-11-24 22:55:26 +08:00
|
|
|
unsigned getMemAccessSize(const MachineInstr* MI) const;
|
|
|
|
|
int getMinValue(const MachineInstr *MI) const;
|
2013-03-02 01:37:13 +08:00
|
|
|
short getNonExtOpcode(const MachineInstr *MI) const;
|
2015-06-12 03:30:37 +08:00
|
|
|
bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
|
|
|
|
|
unsigned &PredRegPos, unsigned &PredRegFlags) const;
|
2015-12-15 05:32:25 +08:00
|
|
|
short getPseudoInstrPair(const MachineInstr *MI) const;
|
2015-11-24 22:55:26 +08:00
|
|
|
short getRegForm(const MachineInstr *MI) const;
|
|
|
|
|
unsigned getSize(const MachineInstr *MI) const;
|
|
|
|
|
uint64_t getType(const MachineInstr* MI) const;
|
|
|
|
|
unsigned getUnits(const MachineInstr* MI) const;
|
|
|
|
|
unsigned getValidSubTargets(const unsigned Opcode) const;
|
|
|
|
|
|
2011-12-13 05:14:40 +08:00
|
|
|
|
2015-11-24 22:55:26 +08:00
|
|
|
/// getInstrTimingClassLatency - Compute the instruction latency of a given
|
|
|
|
|
/// instruction using Timing Class information, if available.
|
|
|
|
|
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
|
|
|
|
|
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void immediateExtend(MachineInstr *MI) const;
|
|
|
|
|
bool invertAndChangeJumpTarget(MachineInstr* MI,
|
|
|
|
|
MachineBasicBlock* NewTarget) const;
|
|
|
|
|
void genAllInsnTimingClasses(MachineFunction &MF) const;
|
|
|
|
|
bool reversePredSense(MachineInstr* MI) const;
|
|
|
|
|
unsigned reversePrediction(unsigned Opcode) const;
|
|
|
|
|
bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
|
2011-12-13 05:14:40 +08:00
|
|
|
};
|
|
|
|
|
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2011-12-13 05:14:40 +08:00
|
|
|
|
|
|
|
|
#endif
|
