forked from OSchip/llvm-project
241 lines
6.9 KiB
C
241 lines
6.9 KiB
C
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//===--- HexagonBlockRanges.h ---------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGON_BLOCK_RANGES_H
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#define HEXAGON_BLOCK_RANGES_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/MC/MCRegisterInfo.h" // For MCPhysReg.
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#include <map>
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#include <set>
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#include <vector>
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namespace llvm {
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class Function;
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class HexagonSubtarget;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MCInstrDesc;
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class raw_ostream;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class Type;
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}
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using namespace llvm;
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struct HexagonBlockRanges {
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HexagonBlockRanges(MachineFunction &MF);
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struct RegisterRef {
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unsigned Reg, Sub;
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bool operator<(RegisterRef R) const {
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return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
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}
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};
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typedef std::set<RegisterRef> RegisterSet;
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// This is to represent an "index", which is an abstraction of a position
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// of an instruction within a basic block.
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class IndexType {
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public:
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enum : unsigned {
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None = 0,
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Entry = 1,
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Exit = 2,
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First = 11 // 10th + 1st
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};
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static bool isInstr(IndexType X) { return X.Index >= First; }
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IndexType() : Index(None) {}
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IndexType(unsigned Idx) : Index(Idx) {}
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operator unsigned() const;
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bool operator== (unsigned x) const;
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bool operator== (IndexType Idx) const;
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bool operator!= (unsigned x) const;
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bool operator!= (IndexType Idx) const;
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IndexType operator++ ();
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bool operator< (unsigned Idx) const;
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bool operator< (IndexType Idx) const;
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bool operator<= (IndexType Idx) const;
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private:
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bool operator> (IndexType Idx) const;
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bool operator>= (IndexType Idx) const;
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unsigned Index;
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};
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// A range of indices, essentially a representation of a live range.
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// This is also used to represent "dead ranges", i.e. ranges where a
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// register is dead.
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class IndexRange : public std::pair<IndexType,IndexType> {
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public:
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IndexRange() : Fixed(false), TiedEnd(false) {}
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IndexRange(IndexType Start, IndexType End, bool F = false, bool T = false)
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: std::pair<IndexType,IndexType>(Start, End), Fixed(F), TiedEnd(T) {}
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IndexType start() const { return first; }
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IndexType end() const { return second; }
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bool operator< (const IndexRange &A) const {
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return start() < A.start();
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}
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bool overlaps(const IndexRange &A) const;
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bool contains(const IndexRange &A) const;
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void merge(const IndexRange &A);
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bool Fixed; // Can be renamed? "Fixed" means "no".
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bool TiedEnd; // The end is not a use, but a dead def tied to a use.
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private:
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void setStart(const IndexType &S) { first = S; }
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void setEnd(const IndexType &E) { second = E; }
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};
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// A list of index ranges. This represents liveness of a register
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// in a basic block.
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class RangeList : public std::vector<IndexRange> {
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public:
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void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd) {
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push_back(IndexRange(Start, End, Fixed, TiedEnd));
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}
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void add(const IndexRange &Range) {
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push_back(Range);
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}
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void include(const RangeList &RL);
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void unionize(bool MergeAdjacent = false);
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void subtract(const IndexRange &Range);
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private:
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void addsub(const IndexRange &A, const IndexRange &B);
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};
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class InstrIndexMap {
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public:
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InstrIndexMap(MachineBasicBlock &B);
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MachineInstr *getInstr(IndexType Idx) const;
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IndexType getIndex(MachineInstr *MI) const;
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MachineBasicBlock &getBlock() const { return Block; }
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IndexType getPrevIndex(IndexType Idx) const;
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IndexType getNextIndex(IndexType Idx) const;
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void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI);
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friend raw_ostream &operator<< (raw_ostream &OS, const InstrIndexMap &Map);
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IndexType First, Last;
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private:
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MachineBasicBlock &Block;
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std::map<IndexType,MachineInstr*> Map;
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};
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typedef std::map<RegisterRef,RangeList> RegToRangeMap;
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RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap);
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RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap);
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static RegisterSet expandToSubRegs(RegisterRef R,
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const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
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struct PrintRangeMap {
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PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I)
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: Map(M), TRI(I) {}
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friend raw_ostream &operator<< (raw_ostream &OS, const PrintRangeMap &P);
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private:
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const RegToRangeMap ⤅
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const TargetRegisterInfo &TRI;
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};
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private:
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RegisterSet getLiveIns(const MachineBasicBlock &B);
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void computeInitialLiveRanges(InstrIndexMap &IndexMap,
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RegToRangeMap &LiveMap);
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MachineFunction &MF;
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const HexagonSubtarget &HST;
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const TargetInstrInfo &TII;
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const TargetRegisterInfo &TRI;
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BitVector Reserved;
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};
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inline HexagonBlockRanges::IndexType::operator unsigned() const {
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assert(Index >= First);
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return Index;
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}
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inline bool HexagonBlockRanges::IndexType::operator== (unsigned x) const {
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return Index == x;
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}
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inline bool HexagonBlockRanges::IndexType::operator== (IndexType Idx) const {
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return Index == Idx.Index;
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}
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inline bool HexagonBlockRanges::IndexType::operator!= (unsigned x) const {
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return Index != x;
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}
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inline bool HexagonBlockRanges::IndexType::operator!= (IndexType Idx) const {
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return Index != Idx.Index;
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}
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inline
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HexagonBlockRanges::IndexType HexagonBlockRanges::IndexType::operator++ () {
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assert(Index != None);
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assert(Index != Exit);
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if (Index == Entry)
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Index = First;
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else
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++Index;
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return *this;
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}
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inline bool HexagonBlockRanges::IndexType::operator< (unsigned Idx) const {
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return operator< (IndexType(Idx));
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}
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inline bool HexagonBlockRanges::IndexType::operator< (IndexType Idx) const {
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// !(x < x).
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if (Index == Idx.Index)
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return false;
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// !(None < x) for all x.
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// !(x < None) for all x.
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if (Index == None || Idx.Index == None)
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return false;
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// !(Exit < x) for all x.
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// !(x < Entry) for all x.
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if (Index == Exit || Idx.Index == Entry)
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return false;
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// Entry < x for all x != Entry.
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// x < Exit for all x != Exit.
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if (Index == Entry || Idx.Index == Exit)
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return true;
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return Index < Idx.Index;
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}
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inline bool HexagonBlockRanges::IndexType::operator<= (IndexType Idx) const {
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return operator==(Idx) || operator<(Idx);
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}
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raw_ostream &operator<< (raw_ostream &OS, HexagonBlockRanges::IndexType Idx);
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raw_ostream &operator<< (raw_ostream &OS,
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const HexagonBlockRanges::IndexRange &IR);
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raw_ostream &operator<< (raw_ostream &OS,
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const HexagonBlockRanges::RangeList &RL);
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raw_ostream &operator<< (raw_ostream &OS,
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const HexagonBlockRanges::InstrIndexMap &M);
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raw_ostream &operator<< (raw_ostream &OS,
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const HexagonBlockRanges::PrintRangeMap &P);
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#endif
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