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llvm-project/llvm/test/CodeGen/PowerPC/pr27078.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s
[PPC] Enable shuffling of VSX vectors This patch fixes PR27078 by enabling shuffling of vectors if VSX is available. llvm-svn: 268064
2016-04-30 01:00:54 +08:00
define <4 x float> @bar(float* %p, float* %q) {
%1 = bitcast float* %p to <12 x float>*
%2 = bitcast float* %q to <12 x float>*
%3 = load <12 x float>, <12 x float>* %1, align 16
%4 = load <12 x float>, <12 x float>* %2, align 16
%5 = fsub <12 x float> %4, %3
%6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
ret <4 x float> %6
[DAG] Generalize build_vector -> vector_shuffle combine for more than 2 inputs This generalizes the build_vector -> vector_shuffle combine to support any number of inputs. The idea is to create a binary tree of shuffles, where the first layer performs pairwise shuffles of the input vectors placing each input element into the correct lane, and the rest of the tree blends these shuffles together. This doesn't try to be smart and create any sort of "optimal" shuffles. The assumption is that even a "poor" shuffle sequence is better than extracting and inserting the elements one by one. Differential Revision: https://reviews.llvm.org/D24683 llvm-svn: 283480
2016-10-07 02:58:24 +08:00
; CHECK: vsldoi
Make test slightly more explicit. NFC. llvm-svn: 281759
2016-09-17 02:20:43 +08:00
; CHECK-NEXT: vmrghw
[DAG] Generalize build_vector -> vector_shuffle combine for more than 2 inputs This generalizes the build_vector -> vector_shuffle combine to support any number of inputs. The idea is to create a binary tree of shuffles, where the first layer performs pairwise shuffles of the input vectors placing each input element into the correct lane, and the rest of the tree blends these shuffles together. This doesn't try to be smart and create any sort of "optimal" shuffles. The assumption is that even a "poor" shuffle sequence is better than extracting and inserting the elements one by one. Differential Revision: https://reviews.llvm.org/D24683 llvm-svn: 283480
2016-10-07 02:58:24 +08:00
; CHECK-NEXT: vmrglw
; CHECK-NEXT: vsldoi
; CHECK-NEXT: vsldoi
Make test slightly more explicit. NFC. llvm-svn: 281759
2016-09-17 02:20:43 +08:00
; CHECK-NEXT: vsldoi
; CHECK-NEXT: blr
[PPC] Enable shuffling of VSX vectors This patch fixes PR27078 by enabling shuffling of vectors if VSX is available. llvm-svn: 268064
2016-04-30 01:00:54 +08:00
}