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llvm-project/llvm/test/CodeGen/Mips/mips64fpldst.ll

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[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
@f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8
@f1 = common global float 0.000000e+00, align 4
@d1 = common global double 0.000000e+00, align 8
define float @funcfl1() nounwind readonly {
entry:
; CHECK-N64: funcfl1
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
; CHECK-N32: funcfl1
Reapply 154038 without the failing test. llvm-svn: 154062
2012-04-05 06:16:36 +08:00
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load float, float* @f0, align 4
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
ret float %0
}
define double @funcfl2() nounwind readonly {
entry:
; CHECK-N64: funcfl2
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
; CHECK-N32: funcfl2
Reapply 154038 without the failing test. llvm-svn: 154062
2012-04-05 06:16:36 +08:00
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load double, double* @d0, align 8
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
ret double %0
}
define void @funcfs1() nounwind {
entry:
; CHECK-N64: funcfs1
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
; CHECK-N32: funcfs1
Reapply 154038 without the failing test. llvm-svn: 154062
2012-04-05 06:16:36 +08:00
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load float, float* @f1, align 4
store float %0, float* @f0, align 4
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
ret void
}
define void @funcfs2() nounwind {
entry:
; CHECK-N64: funcfs2
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
; CHECK-N32: funcfs2
Reapply 154038 without the failing test. llvm-svn: 154062
2012-04-05 06:16:36 +08:00
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load double, double* @d1, align 8
store double %0, double* @d0, align 8
Test cases for 64-bit load and store instructions. llvm-svn: 141631
2011-10-11 09:52:31 +08:00
ret void
}