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llvm-project/llvm/test/CodeGen/Mips/llvm-ir/mul.ll

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[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32
; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32
; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R6
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; RUN: FileCheck %s -check-prefix=MM64R6
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
entry:
; ALL-LABEL: mul_i1:
; M2: mult $4, $5
; M2: mflo $[[T0:[0-9]+]]
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; M2: andi $[[T0]], $[[T0]], 1
; M2: negu $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; 32R1-R5: andi $[[T0]], $[[T0]], 1
; 32R1-R5: negu $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 32R6: mul $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; 32R6: andi $[[T0]], $[[T0]], 1
; 32R6: negu $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; M4: mult $4, $5
; M4: mflo $[[T0:[0-9]+]]
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; M4: andi $[[T0]], $[[T0]], 1
; M4: negu $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; 64R1-R5: andi $[[T0]], $[[T0]], 1
; 64R1-R5: negu $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 64R6: mul $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; 64R6: andi $[[T0]], $[[T0]], 1
; 64R6: negu $2, $[[T0]]
; MM64R6: mul $[[T0:[0-9]+]], $4, $5
; MM64R6: andi16 $[[T0]], $[[T0]], 1
; MM64R6: li16 $[[T1:[0-9]+]], 0
; MM64R6: subu16 $2, $[[T1]], $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
; MM32: mul $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM32: andi16 $[[T0]], $[[T0]], 1
; MM32: li16 $[[T1:[0-9]+]], 0
; MM32: subu16 $2, $[[T1]], $[[T0]]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
%r = mul i1 %a, %b
ret i1 %r
}
define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
entry:
; ALL-LABEL: mul_i8:
; M2: mult $4, $5
; M2: mflo $[[T0:[0-9]+]]
; M2: sll $[[T0]], $[[T0]], 24
; M2: sra $2, $[[T0]], 24
; 32R1: mul $[[T0:[0-9]+]], $4, $5
; 32R1: sll $[[T0]], $[[T0]], 24
; 32R1: sra $2, $[[T0]], 24
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
; 32R2-R5: seb $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: seb $2, $[[T0]]
; M4: mult $4, $5
; M4: mflo $[[T0:[0-9]+]]
; M4: sll $[[T0]], $[[T0]], 24
; M4: sra $2, $[[T0]], 24
; 64R1: mul $[[T0:[0-9]+]], $4, $5
; 64R1: sll $[[T0]], $[[T0]], 24
; 64R1: sra $2, $[[T0]], 24
; 64R2: mul $[[T0:[0-9]+]], $4, $5
; 64R2: seb $2, $[[T0]]
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seb $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM64R6: mul $[[T0:[0-9]+]], $4, $5
; MM64R6: seb $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seb $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
%r = mul i8 %a, %b
ret i8 %r
}
define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
entry:
; ALL-LABEL: mul_i16:
; M2: mult $4, $5
; M2: mflo $[[T0:[0-9]+]]
; M2: sll $[[T0]], $[[T0]], 16
; M2: sra $2, $[[T0]], 16
; 32R1: mul $[[T0:[0-9]+]], $4, $5
; 32R1: sll $[[T0]], $[[T0]], 16
; 32R1: sra $2, $[[T0]], 16
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
; 32R2-R5: seh $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: seh $2, $[[T0]]
; M4: mult $4, $5
; M4: mflo $[[T0:[0-9]+]]
; M4: sll $[[T0]], $[[T0]], 16
; M4: sra $2, $[[T0]], 16
; 64R1: mul $[[T0:[0-9]+]], $4, $5
; 64R1: sll $[[T0]], $[[T0]], 16
; 64R1: sra $2, $[[T0]], 16
; 64R2: mul $[[T0:[0-9]+]], $4, $5
; 64R2: seh $2, $[[T0]]
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seh $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM64R6: mul $[[T0:[0-9]+]], $4, $5
; MM64R6: seh $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seh $2, $[[T0]]
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
%r = mul i16 %a, %b
ret i16 %r
}
define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: mul_i32:
; M2: mult $4, $5
; M2: mflo $2
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 32R1-R5: mul $2, $4, $5
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 32R6: mul $2, $4, $5
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 64R1-R5: mul $2, $4, $5
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 64R6: mul $2, $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM64R6: mul $2, $4, $5
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
; MM32: mul $2, $4, $5
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
%r = mul i32 %a, %b
ret i32 %r
}
define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: mul_i64:
; M2: mult $4, $7
; M2: mflo $[[T0:[0-9]+]]
; M2: mult $5, $6
; M2: mflo $[[T1:[0-9]+]]
; M2: multu $5, $7
; M2: mflo $3
; M2: mfhi $4
; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
; M2: addu $2, $[[T2]], $[[T0]]
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 32R1-R5: multu $5, $7
; 32R1-R5: mflo $3
; 32R1-R5: mfhi $[[T0:[0-9]+]]
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6
; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]]
; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7
; 32R1-R5: addu $2, $[[T0]], $[[T2]]
; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6
; 32R6: muhu $[[T1:[0-9]+]], $5, $7
; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7
; 32R6: addu $2, $[[T0]], $[[T2]]
[mips] MIPSR6 Instruction itineraries Summary: Defines instruction itineraries for common MIPSR6 instructions. Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17198 llvm-svn: 263229
2016-03-11 21:05:06 +08:00
; 32R6-DAG: mul $3, $5, $7
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; M4: dmult $4, $5
; M4: mflo $2
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 64R1-R5: dmult $4, $5
; 64R1-R5: mflo $2
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
; 64R6: dmul $2, $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM64R6: dmul $2, $4, $5
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
; MM32R3: multu $[[T0:[0-9]+]], $7
; MM32R3: mflo $[[T1:[0-9]+]]
; MM32R3: mfhi $[[T2:[0-9]+]]
; MM32R3: mul $[[T0]], $[[T0]], $6
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; MM32R3: addu16 $2, $[[T2]], $[[T0]]
; MM32R3: mul $[[T3:[0-9]+]], $4, $7
; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; MM32R6: mul $[[T0:[0-9]+]], $5, $6
; MM32R6: muhu $[[T1:[0-9]+]], $5, $7
; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]]
; MM32R6: mul $[[T3:[0-9]+]], $4, $7
; MM32R6: addu16 $2, $[[T2]], $[[T3]]
; MM32R6: mul $[[T1]], $5, $7
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
[mips] Add preliminary support for the MIPS II target. Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
2014-11-11 19:43:55 +08:00
%r = mul i64 %a, %b
ret i64 %r
}
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: mul_i128:
; GP32: lw $25, %call16(__multi3)($gp)
; GP64-NOT-R6: dmult $4, $7
; GP64-NOT-R6: mflo $[[T0:[0-9]+]]
; GP64-NOT-R6: dmult $5, $6
; GP64-NOT-R6: mflo $[[T1:[0-9]+]]
; GP64-NOT-R6: dmultu $5, $7
; GP64-NOT-R6: mflo $3
; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]
; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
[mips] MIPSR6 Instruction itineraries Summary: Defines instruction itineraries for common MIPSR6 instructions. Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17198 llvm-svn: 263229
2016-03-11 21:05:06 +08:00
; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
[mips] MIPSR6 Instruction itineraries Summary: Defines instruction itineraries for common MIPSR6 instructions. Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17198 llvm-svn: 263229
2016-03-11 21:05:06 +08:00
; 64R6: daddu $2, $[[T1]], $[[T0]]
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; 64R6-DAG: dmul $3, $5, $7
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7
; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
; MM64R6: daddu $2, $[[T1]], $[[T0]]
; MM64R6-DAG: dmul $3, $5, $7
[mips] Preparatory work for a generic scheduler Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
2016-08-24 21:00:47 +08:00
; MM32: lw $25, %call16(__multi3)($16)
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
2016-05-06 16:24:14 +08:00
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
%r = mul i128 %a, %b
ret i128 %r
}