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llvm-project/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll

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[mips] Missing test case Add missing testcase from r272666. llvm-svn: 272784
2016-06-15 21:49:58 +08:00
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32
[mips] Recommit: "N64 static relocation model support" This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
2017-01-27 19:36:52 +08:00
; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | \
[mips] Missing test case Add missing testcase from r272666. llvm-svn: 272784
2016-06-15 21:49:58 +08:00
; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-MIPSN32
; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate
; (d)subu and (d)addu rather than just (d)addu. The (d)subu sequences are
; generally shorter as the constant that has to be materialized is smaller.
define i32 @main() {
entry:
%z = alloca [1048576 x i8], align 1
%arraydecay = getelementptr inbounds [1048576 x i8], [1048576 x i8]* %z, i32 0, i32 0
%call = call i32 @foo(i8* %arraydecay)
ret i32 0
; CHECK-LABEL: main
; CHECK-MIPS32: lui $[[R0:[0-9]+]], 16
; CHECK-MIPS32: addiu $[[R0]], $[[R0]], 24
; CHECK-MIPS32: subu $sp, $sp, $[[R0]]
; CHECK-MIPS32: lui $[[R1:[0-9]+]], 16
; CHECK-MIPS32: addiu $[[R1]], $[[R1]], 24
; CHECK-MIPS32: addu $sp, $sp, $[[R1]]
; CHECK-MIPS64: lui $[[R0:[0-9]+]], 1
; CHECK-MIPS64: daddiu $[[R0]], $[[R0]], 32
; CHECK-MIPS64: dsubu $sp, $sp, $[[R0]]
; FIXME:
; These are here to match other lui's used in address computations. We need to
; investigate why address computations are not CSE'd. Or implement it.
; CHECK-MIPS64: lui
; CHECK-MIPS64: lui
; CHECK-MIPS64: lui
; CHECK-MIPS64: lui
; CHECK-MIPS64: lui $[[R1:[0-9]+]], 16
; CHECK-MIPS64: daddiu $[[R1]], $[[R1]], 32
; CHECK-MIPS64: daddu $sp, $sp, $[[R1]]
; CHECK-MIPSN32: lui $[[R0:[0-9]+]], 16
; CHECK-MIPSN32: addiu $[[R0]], $[[R0]], 16
; CHECK-MIPSN32: subu $sp, $sp, $[[R0]]
; CHECK-MIPSN32: lui $[[R1:[0-9]+]], 16
; CHECK-MIPSN32: addiu $[[R1]], $[[R1]], 16
; CHECK-MIPSN32: addu $sp, $sp, $[[R1]]
}
declare i32 @foo(i8*)