2016-08-02 03:36:39 +08:00
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; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
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2016-08-25 21:35:48 +08:00
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; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
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2016-08-02 03:36:39 +08:00
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; generate .long XXXX which is a vector debug print instruction.
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; CHECK: .long 0x1dffe0
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2016-08-25 21:35:48 +08:00
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; CHECK: .long 0x1dffe0
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; CHECK: .long 0x1dffe0
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; VSTPRINT: .long 0x1dffe0
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; VSTPRINT-NOT: .long 0x1dffe0
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2016-08-02 03:36:39 +08:00
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @do_vecs(i8* nocapture readonly %a, i8* nocapture readonly %b, i8* nocapture %c) #0 {
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entry:
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%0 = bitcast i8* %a to <16 x i32>*
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%1 = load <16 x i32>, <16 x i32>* %0, align 4, !tbaa !1
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%2 = bitcast i8* %b to <16 x i32>*
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%3 = load <16 x i32>, <16 x i32>* %2, align 4, !tbaa !1
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%4 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %1, <16 x i32> %3)
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%5 = bitcast i8* %c to <16 x i32>*
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store <16 x i32> %4, <16 x i32>* %5, align 4, !tbaa !1
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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!llvm.ident = !{!0}
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!0 = !{!"QuIC LLVM Hexagon Clang version 7.x-pre-unknown"}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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