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llvm-project/llvm/test/MC/ARM/armv8.2a-dotprod-error.s

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[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 17:52:30 +08:00
// RUN: not llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
// RUN: not llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
[ARM] Fix for indexed dot product instruction descriptions The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
2017-09-18 22:17:57 +08:00
// Only indices 0 an 1 should be accepted:
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 17:52:30 +08:00
vudot.u8 d0, d1, d2[2]
vsdot.s8 d0, d1, d2[2]
vudot.u8 q0, q1, d4[2]
vsdot.s8 q0, q1, d4[2]
// CHECK-ERROR: error: invalid operand for instruction
[ARM] Fix for indexed dot product instruction descriptions The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
2017-09-18 22:17:57 +08:00
// CHECK-ERROR: vudot.u8 d0, d1, d2[2]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: vsdot.s8 d0, d1, d2[2]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: vudot.u8 q0, q1, d4[2]
// CHECK-ERROR: ^
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 17:52:30 +08:00
// CHECK-ERROR: error: invalid operand for instruction
[ARM] Fix for indexed dot product instruction descriptions The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
2017-09-18 22:17:57 +08:00
// CHECK-ERROR: vsdot.s8 q0, q1, d4[2]
// CHECK-ERROR: ^
// Only the lower 16 D-registers should be accepted:
vudot.u8 q0, q1, d16[0]
vsdot.s8 q0, q1, d16[0]
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
// CHECK-ERROR: error: operand must be a register in range [d0, d15]
[ARM] Fix for indexed dot product instruction descriptions The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
2017-09-18 22:17:57 +08:00
// CHECK-ERROR: vudot.u8 q0, q1, d16[0]
// CHECK-ERROR: ^
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
// CHECK-ERROR: error: operand must be a register in range [d0, d15]
[ARM] Fix for indexed dot product instruction descriptions The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
2017-09-18 22:17:57 +08:00
// CHECK-ERROR: vsdot.s8 q0, q1, d16[0]
// CHECK-ERROR: ^