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llvm-project/llvm/test/CodeGen/SystemZ/load-and-test.mir

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[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=postrapseudos %s -o - \
# RUN: | FileCheck %s
#
# Check that integer load and test instructions are not emitted for unsigned
# comparisons unless checking for equality. That would be wrong, since the
# operands are implicitly treated as signed values.
# Not legal: Logical comparison used for >= (CCMask is 10).
# CHECK-LABEL: fun0
# CHECK-NOT: lt
---
name: fun0
tracksRegLiveness: true
body: |
bb.0 ():
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r1d
renamable $r0l = L $r1d, 0, $noreg
CLFIMux killed renamable $r0l, 0, implicit-def $cc
BRC 14, 10, %bb.2, implicit $cc
[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
bb.1 ():
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0l
ST killed renamable $r0l, $r15d, 164, $noreg
[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
bb.2 ():
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0l
ST killed renamable $r0l, $r15d, 164, $noreg
[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
Return
...
# Legal: Logical comparison used for == (CCMask is 8).
# CHECK-LABEL: fun1
# CHECK: lt
---
name: fun1
tracksRegLiveness: true
body: |
bb.0 ():
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r1d
renamable $r0l = L $r1d, 0, $noreg
CLFIMux killed renamable $r0l, 0, implicit-def $cc
BRC 14, 8, %bb.2, implicit $cc
[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
bb.1 ():
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0l
ST killed renamable $r0l, $r15d, 164, $noreg
[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
bb.2 ():
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0l
ST killed renamable $r0l, $r15d, 164, $noreg
[SystemZ] Check for legality before doing LOAD AND TEST transformations. Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
2018-01-15 23:41:26 +08:00
Return
...