forked from OSchip/llvm-project
29 lines
958 B
LLVM
29 lines
958 B
LLVM
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; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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target triple = "hexagon"
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@g0 = common global <16 x i32> zeroinitializer, align 64
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@g1 = common global <32 x i32> zeroinitializer, align 128
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@g2 = common global <32 x i32> zeroinitializer, align 128
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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%v0 = load <16 x i32>, <16 x i32>* @g0, align 64
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%v1 = load <32 x i32>, <32 x i32>* @g1, align 128
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%v2 = call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v1)
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%v3 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v0, <16 x i32> %v2)
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store <32 x i32> %v3, <32 x i32>* @g2, align 128
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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