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llvm-project/llvm/test/CodeGen/Hexagon/bank-conflict-load.mir

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[Hexagon] Check for potential bank conflicts in post-RA scheduling Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
2017-08-29 02:36:21 +08:00
# RUN: llc -march=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# The two loads from %a ($r0) can cause a bank conflict. Check that they
[Hexagon] Check for potential bank conflicts in post-RA scheduling Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
2017-08-29 02:36:21 +08:00
# are not scheduled next to each other.
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: L2_loadri_io $r0, 8
# CHECK: L2_loadri_io killed $r1, 0
# CHECK: L2_loadri_io killed $r0, 12
[Hexagon] Check for potential bank conflicts in post-RA scheduling Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
2017-08-29 02:36:21 +08:00
--- |
define void @foo(i32* %a, i32* %b) {
ret void
}
...
---
name: foo
tracksRegLiveness: true
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0, $r1
[Hexagon] Check for potential bank conflicts in post-RA scheduling Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
2017-08-29 02:36:21 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$r2 = L2_loadri_io $r0, 8 :: (load 4 from %ir.a)
$r3 = L2_loadri_io killed $r0, 12 :: (load 4 from %ir.a)
$r4 = L2_loadri_io killed $r1, 0 :: (load 4 from %ir.b)
[Hexagon] Check for potential bank conflicts in post-RA scheduling Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
2017-08-29 02:36:21 +08:00
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