forked from OSchip/llvm-project
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
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; RUN: llc -march=hexagon -mattr=-packets -hexagon-check-bank-conflict=0 < %s | FileCheck %s
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; Do not check stores. They undergo some optimizations in the DAG combiner
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; resulting in getting out of order. There is likely little that can be
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; done to keep the original order.
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target triple = "hexagon"
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%s.0 = type { i32, i32, i32 }
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; Function Attrs: nounwind
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define void @f0(%s.0* %a0, %s.0* %a1) #0 {
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b0:
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; CHECK: = memw({{.*}}+#0)
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; CHECK: = memw({{.*}}+#4)
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; CHECK: = memw({{.*}}+#8)
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%v0 = alloca %s.0*, align 4
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%v1 = alloca %s.0*, align 4
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store %s.0* %a0, %s.0** %v0, align 4
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store %s.0* %a1, %s.0** %v1, align 4
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%v2 = load %s.0*, %s.0** %v0, align 4
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%v3 = load %s.0*, %s.0** %v1, align 4
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%v4 = bitcast %s.0* %v2 to i8*
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%v5 = bitcast %s.0* %v3 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %v4, i8* align 4 %v5, i32 12, i1 false)
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) #1
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attributes #0 = { nounwind }
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attributes #1 = { argmemonly nounwind }
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