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llvm-project/llvm/test/CodeGen/AArch64/sdivpow2.ll

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[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ISEL
; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,FAST
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
define i32 @test1(i32 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test1:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #7 // =7
; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: asr w0, w8, #3
; CHECK-NEXT: ret
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
%div = sdiv i32 %x, 8
ret i32 %div
}
define i32 @test2(i32 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test2:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #7 // =7
; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: neg w0, w8, asr #3
; CHECK-NEXT: ret
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
%div = sdiv i32 %x, -8
ret i32 %div
}
define i32 @test3(i32 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test3:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #31 // =31
; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: asr w0, w8, #5
; CHECK-NEXT: ret
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
%div = sdiv i32 %x, 32
ret i32 %div
}
define i64 @test4(i64 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test4:
; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #7 // =7
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #3
; CHECK-NEXT: ret
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
%div = sdiv i64 %x, 8
ret i64 %div
}
define i64 @test5(i64 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test5:
; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #7 // =7
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: neg x0, x8, asr #3
; CHECK-NEXT: ret
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
%div = sdiv i64 %x, -8
ret i64 %div
}
define i64 @test6(i64 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test6:
; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #63 // =63
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #6
; CHECK-NEXT: ret
[AArch64] Lower sdiv x, pow2 using add + select + shift. The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
2014-07-23 22:57:52 +08:00
%div = sdiv i64 %x, 64
ret i64 %div
}
[AArch64] Fix miscompile of sdiv-by-power-of-2. When the constant divisor was larger than 32bits, then the optimized code generated for the AArch64 backend would emit the wrong code, because the shift was defined as a shift of a 32bit constant '(1<<Lg2(divisor))' and we would loose the upper 32bits. This fixes rdar://problem/18678801. llvm-svn: 219934
2014-10-17 00:41:15 +08:00
define i64 @test7(i64 %x) {
[AArch64] Regenerate SDIV tests Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
2018-07-11 18:39:50 +08:00
; CHECK-LABEL: test7:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x8, xzr, #0xffffffffffff
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #48
; CHECK-NEXT: ret
[AArch64] Fix miscompile of sdiv-by-power-of-2. When the constant divisor was larger than 32bits, then the optimized code generated for the AArch64 backend would emit the wrong code, because the shift was defined as a shift of a 32bit constant '(1<<Lg2(divisor))' and we would loose the upper 32bits. This fixes rdar://problem/18678801. llvm-svn: 219934
2014-10-17 00:41:15 +08:00
%div = sdiv i64 %x, 281474976710656
ret i64 %div
}