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llvm-project/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll

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[AArch64] Add test case for fusion of literal generation Add test case from https://reviews.llvm.org/D28698 that was somehow lost in transit. llvm-svn: 295775
2017-02-22 06:16:09 +08:00
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=-fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKDONT
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
[AArch64] Add pipeline model for Exynos M3 Add the scheduling and cost model for Exynos M3. Differential revision: https://reviews.llvm.org/D42387 llvm-svn: 323773
2018-01-30 23:40:16 +08:00
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
[AArch64, ARM] Add support for Samsung Exynos M4 Create a separate feature set for Exynos M4 and add test cases. llvm-svn: 334115
2018-06-07 02:56:00 +08:00
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
[AArch64] Add test case for fusion of literal generation Add test case from https://reviews.llvm.org/D28698 that was somehow lost in transit. llvm-svn: 295775
2017-02-22 06:16:09 +08:00
@g = common local_unnamed_addr global i8* null, align 8
define i8* @litp(i32 %a, i32 %b) {
entry:
%add = add nsw i32 %b, %a
%idx.ext = sext i32 %add to i64
%add.ptr = getelementptr i8, i8* bitcast (i8* (i32, i32)* @litp to i8*), i64 %idx.ext
store i8* %add.ptr, i8** @g, align 8
ret i8* %add.ptr
; CHECK-LABEL: litp:
; CHECK: adrp [[R:x[0-9]+]], litp
; CHECKDONT-NEXT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECKFUSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp
}
define i32 @liti(i32 %a, i32 %b) {
entry:
%add = add i32 %a, -262095121
%add1 = add i32 %add, %b
ret i32 %add1
; CHECK-LABEL: liti:
; CHECK: mov [[R:w[0-9]+]], {{#[0-9]+}}
; CHECKDONT-NEXT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECKFUSE-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
}
; Function Attrs: norecurse nounwind readnone
define i64 @litl(i64 %a, i64 %b) {
entry:
%add = add i64 %a, 2208998440489107183
%add1 = add i64 %add, %b
ret i64 %add1
; CHECK-LABEL: litl:
; CHECK: mov [[R:x[0-9]+]], {{#[0-9]+}}
; CHECK-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
; CHECK: movk [[R]], {{#[0-9]+}}, lsl #32
; CHECKDONT-NEXT: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
; CHECKFUSE-NEXT: movk [[R]], {{#[0-9]+}}, lsl #48
}
[AArch64] Optimize floating point materialization This patch follows some ideas from r352866 to optimize the floating point materialization even further. It changes isFPImmLegal to considere up to 2 mov instruction or up to 5 in case subtarget has fused literals. The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but the mov+fmov sequence is always better because of the reduced d-cache pressure. The timings are still the same if you consider movw+movk+fmov vs. adrp+ldr will be fused (although one instruction longer). Reviewers: efriedma Differential Revision: https://reviews.llvm.org/D58460 llvm-svn: 356390
2019-03-19 02:45:57 +08:00
; Function Attrs: norecurse nounwind readnone
define double @litf() {
entry:
ret double 0x400921FB54442D18
; CHECK-LABEL: litf:
; CHECK-DONT: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
; CHECK-DONT-NEXT: ldr {{d[0-9]+}}, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
; CHECK-FUSE: mov [[R:x[0-9]+]], #11544
; CHECK-FUSE: movk [[R]], #21572, lsl #16
; CHECK-FUSE: movk [[R]], #8699, lsl #32
; CHECK-FUSE: movk [[R]], #16393, lsl #48
; CHECK-FUSE: fmov {{d[0-9]+}}, [[R]]
}