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llvm-project/clang/test/CodeGen/ms-inline-asm-avx512.c

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-inline-asm][X86] Add ability to use AVX512 in MS inline asm Defined the new AVX512 registers in clang inline asm. Fixed a bug in the MC subtarget info creation during the parsing of MS asm statement - now it receives the actual CPU and target features information. Differential Revision: http://reviews.llvm.org/D16757 llvm-svn: 259639
2016-02-03 19:32:08 +08:00
// REQUIRES: x86-registered-target
[ms-inline-asm] Use the frontend size only for ambiguous instructions This avoids problems on code like this: char buf[16]; __asm { movups xmm0, [buf] mov [buf], eax } The frontend size in this case (1) is wrong, and the register makes the instruction matching unambiguous. There are also enough bytes available that we shouldn't complain to the user that they are potentially using an incorrectly sized instruction to access the variable. Supersedes D32636 and D26586 and fixes PR28266 llvm-svn: 302179
2017-05-05 02:19:52 +08:00
// RUN: %clang_cc1 %s -triple x86_64-pc-windows-msvc -target-cpu skylake-avx512 -fasm-blocks -emit-llvm -o - | FileCheck %s
-inline-asm][X86] Add ability to use AVX512 in MS inline asm Defined the new AVX512 registers in clang inline asm. Fixed a bug in the MC subtarget info creation during the parsing of MS asm statement - now it receives the actual CPU and target features information. Differential Revision: http://reviews.llvm.org/D16757 llvm-svn: 259639
2016-02-03 19:32:08 +08:00
void t1() {
// CHECK: @t1
// CHECK: call void asm sideeffect inteldialect "vaddpd zmm8, zmm27, zmm6", "~{zmm8},~{dirflag},~{fpsr},~{flags}"()
// CHECK: ret void
__asm {
vaddpd zmm8, zmm27, zmm6
}
}
[ms-inline-asm][AVX512] Add ability to use k registers in MS inline asm + fix bag with curly braces Until now curly braces could only be used in MS inline assembly to mark block start/end. All curly braces were removed completely at a very early stage. This approach caused bugs like: "m{o}v eax, ebx" turned into "mov eax, ebx" without any error. In addition, AVX-512 added special operands (e.g., k registers), which are also surrounded by curly braces that mark them as such. Now, we need to keep the curly braces and identify at a later stage if they are marking block start/end (if so, ignore them), or surrounding special AVX-512 operands (if so, parse them as such). This patch fixes the bug described above and enables the use of AVX-512 special operands. This commit is the the clang part of the patch. The clang part of the review is: http://reviews.llvm.org/D17766 The llvm part of the review is: http://reviews.llvm.org/D17767 Differential Revision: http://reviews.llvm.org/D17766 llvm-svn: 262842
2016-03-08 02:10:25 +08:00
void t2() {
// CHECK: @t2
// CHECK: call void asm sideeffect inteldialect "vaddpd zmm8 {k1}, zmm27, zmm6", "~{zmm8},~{dirflag},~{fpsr},~{flags}"()
// CHECK: ret void
__asm {
vaddpd zmm8 {k1}, zmm27, zmm6
}
}
[ms-inline-asm] Use the frontend size only for ambiguous instructions This avoids problems on code like this: char buf[16]; __asm { movups xmm0, [buf] mov [buf], eax } The frontend size in this case (1) is wrong, and the register makes the instruction matching unambiguous. There are also enough bytes available that we shouldn't complain to the user that they are potentially using an incorrectly sized instruction to access the variable. Supersedes D32636 and D26586 and fixes PR28266 llvm-svn: 302179
2017-05-05 02:19:52 +08:00
void ignore_fe_size() {
Bring r325915 back. The tests that failed on a windows host have been fixed. Original message: Start setting dso_local for COFF. With this there are still some GVs where we don't set dso_local because setGVProperties is never called. I intend to fix that in followup commits. This is just the bare minimum to teach shouldAssumeDSOLocal what it should do for COFF. llvm-svn: 325940
2018-02-24 03:30:48 +08:00
// CHECK-LABEL: define dso_local void @ignore_fe_size()
[ms-inline-asm] Use the frontend size only for ambiguous instructions This avoids problems on code like this: char buf[16]; __asm { movups xmm0, [buf] mov [buf], eax } The frontend size in this case (1) is wrong, and the register makes the instruction matching unambiguous. There are also enough bytes available that we shouldn't complain to the user that they are potentially using an incorrectly sized instruction to access the variable. Supersedes D32636 and D26586 and fixes PR28266 llvm-svn: 302179
2017-05-05 02:19:52 +08:00
char c;
// CHECK: vaddps xmm1, xmm2, $1{1to4}
__asm vaddps xmm1, xmm2, [c]{1to4}
// CHECK: vaddps xmm1, xmm2, $2
__asm vaddps xmm1, xmm2, [c]
// CHECK: mov eax, $3
__asm mov eax, [c]
// CHECK: mov $0, rax
__asm mov [c], rax
}