maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/clang/test/CodeGen/fma4-builtins.c

277 lines
16 KiB
C
Raw Normal View History

[X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted environment since it expects stdlib.h to be available - which is not the case in these internal clang codegen tests). This patch removes this hack and instead passes -ffreestanding to clang cc1. Differential Revision: https://reviews.llvm.org/D24825 llvm-svn: 282581
2016-09-28 19:59:09 +08:00
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +fma4 -emit-llvm -o - -Wall -Werror | FileCheck %s
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
#include <x86intrin.h>
__m128 test_mm_macc_ps(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_macc_ps
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_macc_ps(a, b, c);
}
__m128d test_mm_macc_pd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_macc_pd
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_macc_pd(a, b, c);
}
__m128 test_mm_macc_ss(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_macc_ss
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
// CHECK: insertelement <4 x float> zeroinitializer, float %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_macc_ss(a, b, c);
}
__m128d test_mm_macc_sd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_macc_sd
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
// CHECK: insertelement <2 x double> zeroinitializer, double %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_macc_sd(a, b, c);
}
__m128 test_mm_msub_ps(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_msub_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_msub_ps(a, b, c);
}
__m128d test_mm_msub_pd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_msub_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_msub_pd(a, b, c);
}
__m128 test_mm_msub_ss(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_msub_ss
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
2017-11-26 03:32:12 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0
// CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float [[C]])
// CHECK: insertelement <4 x float> zeroinitializer, float %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_msub_ss(a, b, c);
}
__m128d test_mm_msub_sd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_msub_sd
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
2017-11-26 03:32:12 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0
// CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double [[C]])
// CHECK: insertelement <2 x double> zeroinitializer, double %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_msub_sd(a, b, c);
}
__m128 test_mm_nmacc_ps(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmacc_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmacc_ps(a, b, c);
}
__m128d test_mm_nmacc_pd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmacc_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmacc_pd(a, b, c);
}
__m128 test_mm_nmacc_ss(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmacc_ss
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
2017-11-26 03:32:12 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: [[A:%.+]] = extractelement <4 x float> [[NEG]], i64 0
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: call float @llvm.fma.f32(float [[A]], float %{{.*}}, float %{{.*}})
// CHECK: insertelement <4 x float> zeroinitializer, float %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmacc_ss(a, b, c);
}
__m128d test_mm_nmacc_sd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmacc_sd
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
2017-11-26 03:32:12 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: [[A:%.+]] = extractelement <2 x double> [[NEG]], i64 0
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: call double @llvm.fma.f64(double [[A]], double %{{.*}}, double %{{.*}})
// CHECK: insertelement <2 x double> zeroinitializer, double %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmacc_sd(a, b, c);
}
__m128 test_mm_nmsub_ps(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmsub_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
// CHECK: [[NEG2:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmsub_ps(a, b, c);
}
__m128d test_mm_nmsub_pd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmsub_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
// CHECK: [[NEG2:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmsub_pd(a, b, c);
}
__m128 test_mm_nmsub_ss(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmsub_ss
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
2017-11-26 03:32:12 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
// CHECK: [[NEG2:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: [[A:%.+]] = extractelement <4 x float> [[NEG]], i64 0
// CHECK: extractelement <4 x float> %{{.*}}, i64 0
// CHECK: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0
// CHECK: call float @llvm.fma.f32(float [[A]], float %{{.*}}, float [[C]])
// CHECK: insertelement <4 x float> zeroinitializer, float %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmsub_ss(a, b, c);
}
__m128d test_mm_nmsub_sd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_nmsub_sd
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
2017-11-26 03:32:12 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
// CHECK: [[NEG2:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Implement _builtin_ia32_vfmaddss and _builtin_ia32_vfmaddsd with native IR using llvm.fma intrinsic. This generates some extra zeroing currently, but we should be able to quickly address that with some isel patterns. llvm-svn: 336417
2018-07-06 15:14:47 +08:00
// CHECK: [[A:%.+]] = extractelement <2 x double> [[NEG]], i64 0
// CHECK: extractelement <2 x double> %{{.*}}, i64 0
// CHECK: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0
// CHECK: call double @llvm.fma.f64(double [[A]], double %{{.*}}, double [[C]])
// CHECK: insertelement <2 x double> zeroinitializer, double %{{.*}}, i64 0
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_nmsub_sd(a, b, c);
}
__m128 test_mm_maddsub_ps(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_maddsub_ps
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]]
// CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_maddsub_ps(a, b, c);
}
__m128d test_mm_maddsub_pd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_maddsub_pd
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]]
// CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> <i32 0, i32 3>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_maddsub_pd(a, b, c);
}
__m128 test_mm_msubadd_ps(__m128 a, __m128 b, __m128 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_msubadd_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.+}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]]
// CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
// CHECK: shufflevector <4 x float> [[ADD]], <4 x float> [[SUB]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_msubadd_ps(a, b, c);
}
__m128d test_mm_msubadd_pd(__m128d a, __m128d b, __m128d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm_msubadd_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]]
// CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
// CHECK: shufflevector <2 x double> [[ADD]], <2 x double> [[SUB]], <2 x i32> <i32 0, i32 3>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm_msubadd_pd(a, b, c);
}
__m256 test_mm256_macc_ps(__m256 a, __m256 b, __m256 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_macc_ps
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_macc_ps(a, b, c);
}
__m256d test_mm256_macc_pd(__m256d a, __m256d b, __m256d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_macc_pd
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_macc_pd(a, b, c);
}
__m256 test_mm256_msub_ps(__m256 a, __m256 b, __m256 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_msub_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_msub_ps(a, b, c);
}
__m256d test_mm256_msub_pd(__m256d a, __m256d b, __m256d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_msub_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_msub_pd(a, b, c);
}
__m256 test_mm256_nmacc_ps(__m256 a, __m256 b, __m256 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_nmacc_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_nmacc_ps(a, b, c);
}
__m256d test_mm256_nmacc_pd(__m256d a, __m256d b, __m256d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_nmacc_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_nmacc_pd(a, b, c);
}
__m256 test_mm256_nmsub_ps(__m256 a, __m256 b, __m256 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_nmsub_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
// CHECK: [[NEG2:%.+]] = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_nmsub_ps(a, b, c);
}
__m256d test_mm256_nmsub_pd(__m256d a, __m256d b, __m256d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_nmsub_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.+}}
// CHECK: [[NEG2:%.+]] = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_nmsub_pd(a, b, c);
}
__m256 test_mm256_maddsub_ps(__m256 a, __m256 b, __m256 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_maddsub_ps
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: [[NEG:%.+]] = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]]
// CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_maddsub_ps(a, b, c);
}
__m256d test_mm256_maddsub_pd(__m256d a, __m256d b, __m256d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_maddsub_pd
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
[X86] Lowering FMA intrinsics to native IR (Clang part) This patch replaces all packed (and scalar without rounding mode) fused intrinsics with fmadd/fmaddsub variations. Then fmadd/fmaddsub are lowered to native IR. Patch by tkrupa Reviewers: craig.topper, sroland, spatel, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47444 llvm-svn: 333555
2018-05-30 23:27:49 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_maddsub_pd(a, b, c);
}
__m256 test_mm256_msubadd_ps(__m256 a, __m256 b, __m256 c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_msubadd_ps
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]]
// CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}})
// CHECK: shufflevector <8 x float> [[ADD]], <8 x float> [[SUB]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_msubadd_ps(a, b, c);
}
__m256d test_mm256_msubadd_pd(__m256d a, __m256d b, __m256d c) {
[X86] Stripped backend codegen tests As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
2015-12-03 16:45:21 +08:00
// CHECK-LABEL: test_mm256_msubadd_pd
[X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to combine the negates to create fmsub, fnmadd, and fnmsub. faddsub converting to fsubadd still needs work I think, but should be very doable. This matches what we already do for the masked builtins. This only covers the packed builtins. Scalar builtins will be done after FMA4 is fixed. llvm-svn: 317873
2017-11-10 13:20:32 +08:00
// CHECK: [[NEG:%.+]] = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.+}}
[X86] Use shufflevector instead of a select with a constant mask for fmaddsub/fmsubadd IR emission. Shufflevector is easier to generate and matches what the backend pattern matches without relying on constant selects being turned into shuffles. While I was there I also made the IR regular expressions a little stricter to ensure operand order on the shuffle. llvm-svn: 336388
2018-07-06 04:38:31 +08:00
// CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]]
// CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}})
// CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
Add FMA4 intrinsics. llvm-svn: 147372
2011-12-30 17:15:03 +08:00
return _mm256_msubadd_pd(a, b, c);
}