2014-05-24 20:50:23 +08:00
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//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
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2014-03-29 18:18:08 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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2016-06-16 01:24:52 +08:00
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// Target-independent interfaces which we are implementing.
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2014-03-29 18:18:08 +08:00
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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2014-05-24 20:50:23 +08:00
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// AArch64 Subtarget features.
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2014-03-29 18:18:08 +08:00
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//
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2014-04-15 01:38:00 +08:00
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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2014-04-19 05:22:04 +08:00
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"Enable ARMv8 FP">;
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2014-04-15 01:38:00 +08:00
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
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[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 16:43:19 +08:00
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def FeatureSM4 : SubtargetFeature<
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"sm4", "HasSM4", "true",
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"Enable SM3 and SM4 support", [FeatureNEON]>;
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def FeatureSHA2 : SubtargetFeature<
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"sha2", "HasSHA2", "true",
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"Enable SHA1 and SHA256 support", [FeatureNEON]>;
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def FeatureSHA3 : SubtargetFeature<
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"sha3", "HasSHA3", "true",
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"Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
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def FeatureAES : SubtargetFeature<
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"aes", "HasAES", "true",
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"Enable AES support", [FeatureNEON]>;
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// Crypto has been split up and any combination is now valid (see the
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// crypto defintions above). Also, crypto is now context sensitive:
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// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
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// Therefore, we rely on Clang, the user interacing tool, to pass on the
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// appropriate crypto options. But here in the backend, crypto has very little
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// meaning anymore. We kept the Crypto defintion here for backward
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// compatibility, and now imply features SHA2 and AES, which was the
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// "traditional" meaning of Crypto.
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2014-04-15 01:38:00 +08:00
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 16:43:19 +08:00
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"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
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2014-04-15 01:38:00 +08:00
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2014-04-25 17:25:42 +08:00
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable ARMv8 CRC-32 checksum instructions">;
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2016-06-03 22:03:27 +08:00
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
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2016-12-01 06:25:24 +08:00
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def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
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"Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
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2017-01-17 00:28:43 +08:00
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def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
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"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
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2015-09-02 00:23:45 +08:00
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable ARMv8 PMUv3 Performance Monitors extension">;
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2015-11-26 23:23:32 +08:00
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Full FP16", [FeatureFPARMv8]>;
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2018-08-17 19:29:49 +08:00
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def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
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"Enable FP16 FML instructions", [FeatureFullFP16]>;
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2015-12-01 18:48:51 +08:00
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def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
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"Enable Statistical Profiling extension">;
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2017-07-13 23:19:56 +08:00
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def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
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"Enable Scalable Vector Extension (SVE) instructions">;
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2014-03-29 18:18:08 +08:00
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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2014-05-06 05:50:57 +08:00
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"Has zero-cycle register moves">;
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2018-09-29 03:05:09 +08:00
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def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
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"Has zero-cycle zeroing instructions for generic registers">;
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def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
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"Has zero-cycle zeroing instructions for FP registers">;
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2014-03-29 18:18:08 +08:00
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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2018-09-29 03:05:09 +08:00
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"Has zero-cycle zeroing instructions",
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[FeatureZCZeroingGP, FeatureZCZeroingFP]>;
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2014-03-29 18:18:08 +08:00
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2017-12-18 18:36:00 +08:00
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/// ... but the floating-point version doesn't quite work in rare cases on older
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/// CPUs.
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def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
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"HasZeroCycleZeroingFPWorkaround", "true",
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"The zero-cycle floating-point zeroing instruction has a bug">;
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2015-07-29 22:17:26 +08:00
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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[AArch64] Support reserving x1-7 registers.
Summary:
Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.
Reviewers: javed.absar, phosek, srhines, nickdesaulniers, efriedma
Reviewed By: nickdesaulniers, efriedma
Subscribers: niravd, jfb, manojgupta, nickdesaulniers, jyknight, efriedma, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D48580
llvm-svn: 341706
2018-09-08 04:58:57 +08:00
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foreach i = {1-7,18,20} in
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def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
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"Reserve X"#i#", making it unavailable "
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"as a GPR">;
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2018-06-13 04:00:50 +08:00
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2018-09-23 06:17:50 +08:00
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foreach i = {8-15,18} in
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def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
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"CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
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2016-06-03 02:03:53 +08:00
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def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
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"Use alias analysis during codegen">;
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def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
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"true",
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"balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
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def FeaturePredictableSelectIsExpensive : SubtargetFeature<
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"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
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"Prefer likely predicted branches over selects">;
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def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
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"CustomAsCheapAsMove", "true",
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"Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
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2018-01-30 23:40:22 +08:00
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def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
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"ExynosAsCheapAsMove", "true",
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"Use Exynos specific code in TargetInstrInfo::isAsCheapAsAMove()",
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[FeatureCustomCheapAsMoveHandling]>;
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2016-06-03 02:03:53 +08:00
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def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
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"UsePostRAScheduler", "true", "Schedule again after register allocation">;
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def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
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"Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
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2017-01-25 01:34:31 +08:00
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def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
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"Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
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2016-06-03 02:03:53 +08:00
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2017-08-29 04:48:43 +08:00
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def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
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"true", "STR of Q register with register offset is slow">;
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2016-06-03 02:03:53 +08:00
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def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
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"alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
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"true", "Use alternative pattern for sextload convert to f32">;
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2016-10-05 03:28:21 +08:00
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def FeatureArithmeticBccFusion : SubtargetFeature<
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"arith-bcc-fusion", "HasArithmeticBccFusion", "true",
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"CPU fuses arithmetic+bcc operations">;
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def FeatureArithmeticCbzFusion : SubtargetFeature<
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"arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
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"CPU fuses arithmetic + cbz/cbnz operations">;
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2016-06-03 02:03:53 +08:00
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2018-01-31 00:28:01 +08:00
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def FeatureFuseAddress : SubtargetFeature<
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"fuse-address", "HasFuseAddress", "true",
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"CPU fuses address generation and memory operations">;
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2017-02-01 10:54:39 +08:00
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def FeatureFuseAES : SubtargetFeature<
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"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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2018-09-20 04:50:51 +08:00
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def FeatureFuseCryptoEOR : SubtargetFeature<
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"fuse-crypto-eor", "HasFuseCryptoEOR", "true",
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"CPU fuses AES/PMULL and EOR operations">;
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2018-02-24 03:27:43 +08:00
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def FeatureFuseCCSelect : SubtargetFeature<
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"fuse-csel", "HasFuseCCSelect", "true",
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"CPU fuses conditional select operations">;
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2017-02-01 10:54:42 +08:00
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def FeatureFuseLiterals : SubtargetFeature<
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"fuse-literals", "HasFuseLiterals", "true",
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"CPU fuses literal generation operations">;
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2016-06-03 02:03:53 +08:00
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def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
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"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
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"Disable latency scheduling heuristic">;
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2018-10-25 04:19:09 +08:00
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def FeatureForce32BitJumpTables
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: SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
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"Force jump table entries to be 32-bits wide except at MinSize">;
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2017-08-10 17:52:55 +08:00
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def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
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"Enable support for RCPC extension">;
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2016-10-25 00:14:58 +08:00
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def FeatureUseRSqrt : SubtargetFeature<
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"use-reciprocal-square-root", "UseRSqrt", "true",
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"Use the reciprocal square root approximation">;
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2017-03-28 18:02:56 +08:00
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2017-08-09 22:59:54 +08:00
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def FeatureDotProd : SubtargetFeature<
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"dotprod", "HasDotProd", "true",
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"Enable dot product support">;
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2017-03-28 18:02:56 +08:00
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def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
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"NegativeImmediates", "false",
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"Convert immediates and instructions "
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"to their negated or complemented "
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"equivalent when the immediate does "
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"not fit in the encoding.">;
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2017-04-01 02:16:53 +08:00
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def FeatureLSLFast : SubtargetFeature<
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"lsl-fast", "HasLSLFast", "true",
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"CPU has a fastpath logical shift of up to 3 places">;
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2017-12-15 07:06:18 +08:00
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2018-01-26 05:55:39 +08:00
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def FeatureAggressiveFMA :
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SubtargetFeature<"aggressive-fma",
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"HasAggressiveFMA",
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"true",
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"Enable Aggressive FMA for floating-point.">;
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2018-09-27 17:11:27 +08:00
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def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
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"Enable alternative NZCV format for floating point comparisons">;
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2018-09-27 21:32:06 +08:00
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def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
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"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
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"an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
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2018-09-27 22:05:46 +08:00
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def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
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"true", "Enable architectural speculation restriction" >;
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2018-09-27 21:39:06 +08:00
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def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
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"Enable speculation control barrier" >;
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2018-09-27 21:47:40 +08:00
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def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
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"Enable execution and data prediction invalidation instructions" >;
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2018-09-27 21:53:35 +08:00
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def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
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"true", "Enable Cache Clean to Point of Deep Persistence" >;
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2018-09-27 22:54:33 +08:00
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def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
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"true", "Enable Branch Target Identification" >;
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2018-09-27 22:01:40 +08:00
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def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
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"true", "Enable Random Number generation instructions" >;
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2018-10-02 17:36:28 +08:00
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def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
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"true", "Enable Memory Tagging Extension" >;
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2015-04-01 22:49:29 +08:00
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//===----------------------------------------------------------------------===//
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// Architectures.
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//
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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2017-01-17 00:28:43 +08:00
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"Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
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2015-04-01 22:49:29 +08:00
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2015-11-26 23:23:32 +08:00
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|
|
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
|
2016-06-03 22:03:27 +08:00
|
|
|
"Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
|
2015-11-26 23:23:32 +08:00
|
|
|
|
2017-08-10 17:41:00 +08:00
|
|
|
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
|
2017-08-10 17:52:55 +08:00
|
|
|
"Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
|
2017-08-10 17:41:00 +08:00
|
|
|
|
[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 16:43:19 +08:00
|
|
|
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
|
|
|
|
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>;
|
|
|
|
|
2018-09-27 21:32:06 +08:00
|
|
|
def HasV8_5aOps : SubtargetFeature<
|
|
|
|
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
|
2018-09-27 22:05:46 +08:00
|
|
|
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
|
2018-09-27 22:54:33 +08:00
|
|
|
FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
|
|
|
|
FeatureBranchTargetId]
|
2018-09-27 21:32:06 +08:00
|
|
|
>;
|
2018-09-26 20:48:21 +08:00
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register File Description
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
include "AArch64RegisterInfo.td"
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
|
|
|
include "AArch64RegisterBanks.td"
|
2014-05-24 20:50:23 +08:00
|
|
|
include "AArch64CallingConvention.td"
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Instruction Descriptions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
include "AArch64Schedule.td"
|
|
|
|
include "AArch64InstrInfo.td"
|
2014-03-29 18:18:08 +08:00
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
def AArch64InstrInfo : InstrInfo;
|
2014-03-29 18:18:08 +08:00
|
|
|
|
2016-07-06 05:23:04 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Named operands for MRS/MSR/TLBI/...
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
include "AArch64SystemOperands.td"
|
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2014-05-24 20:50:23 +08:00
|
|
|
// AArch64 Processors supported.
|
2014-03-29 18:18:08 +08:00
|
|
|
//
|
2014-05-24 20:50:23 +08:00
|
|
|
include "AArch64SchedA53.td"
|
2014-06-12 05:06:56 +08:00
|
|
|
include "AArch64SchedA57.td"
|
2014-05-24 20:50:23 +08:00
|
|
|
include "AArch64SchedCyclone.td"
|
2016-11-30 04:00:27 +08:00
|
|
|
include "AArch64SchedFalkor.td"
|
2016-02-12 23:51:51 +08:00
|
|
|
include "AArch64SchedKryo.td"
|
2018-01-30 04:22:24 +08:00
|
|
|
include "AArch64SchedExynosM1.td"
|
2018-01-30 23:40:16 +08:00
|
|
|
include "AArch64SchedExynosM3.td"
|
2017-02-18 02:34:24 +08:00
|
|
|
include "AArch64SchedThunderX.td"
|
2017-03-08 03:42:40 +08:00
|
|
|
include "AArch64SchedThunderX2T99.td"
|
2014-03-29 18:18:08 +08:00
|
|
|
|
2015-12-02 19:53:44 +08:00
|
|
|
def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
|
2016-06-03 02:03:53 +08:00
|
|
|
"Cortex-A35 ARM processors", [
|
2015-12-02 19:53:44 +08:00
|
|
|
FeatureCRC,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon
|
|
|
|
]>;
|
2015-12-02 19:53:44 +08:00
|
|
|
|
2014-04-15 01:38:00 +08:00
|
|
|
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
|
2016-06-03 02:03:53 +08:00
|
|
|
"Cortex-A53 ARM processors", [
|
|
|
|
FeatureBalanceFPOps,
|
2015-09-02 00:23:45 +08:00
|
|
|
FeatureCRC,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureCrypto,
|
|
|
|
FeatureCustomCheapAsMoveHandling,
|
|
|
|
FeatureFPARMv8,
|
2017-05-31 23:50:03 +08:00
|
|
|
FeatureFuseAES,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeatureUseAA
|
|
|
|
]>;
|
2014-04-15 01:38:00 +08:00
|
|
|
|
2017-08-21 16:43:06 +08:00
|
|
|
def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
|
|
|
|
"Cortex-A55 ARM processors", [
|
2017-09-18 22:46:14 +08:00
|
|
|
HasV8_2aOps,
|
2017-08-21 16:43:06 +08:00
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureFuseAES,
|
|
|
|
FeatureNEON,
|
|
|
|
FeatureFullFP16,
|
|
|
|
FeatureDotProd,
|
|
|
|
FeatureRCPC,
|
|
|
|
FeaturePerfMon
|
|
|
|
]>;
|
|
|
|
|
2014-04-15 01:38:00 +08:00
|
|
|
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
|
2016-06-03 02:03:53 +08:00
|
|
|
"Cortex-A57 ARM processors", [
|
|
|
|
FeatureBalanceFPOps,
|
2015-09-02 00:23:45 +08:00
|
|
|
FeatureCRC,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureCrypto,
|
|
|
|
FeatureCustomCheapAsMoveHandling,
|
|
|
|
FeatureFPARMv8,
|
2017-02-01 10:54:39 +08:00
|
|
|
FeatureFuseAES,
|
2017-02-01 10:54:42 +08:00
|
|
|
FeatureFuseLiterals,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive
|
|
|
|
]>;
|
2014-04-15 01:38:00 +08:00
|
|
|
|
[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
llvm-svn: 273277
2016-06-21 23:53:54 +08:00
|
|
|
def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
|
|
|
|
"Cortex-A72 ARM processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
2017-05-15 23:15:22 +08:00
|
|
|
FeatureFuseAES,
|
[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
llvm-svn: 273277
2016-06-21 23:53:54 +08:00
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon
|
|
|
|
]>;
|
|
|
|
|
|
|
|
def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
|
|
|
|
"Cortex-A73 ARM processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
2017-05-31 23:25:25 +08:00
|
|
|
FeatureFuseAES,
|
[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
llvm-svn: 273277
2016-06-21 23:53:54 +08:00
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon
|
|
|
|
]>;
|
|
|
|
|
2017-08-21 16:43:06 +08:00
|
|
|
def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
|
|
|
|
"Cortex-A75 ARM processors", [
|
2017-09-18 22:46:14 +08:00
|
|
|
HasV8_2aOps,
|
2017-08-21 16:43:06 +08:00
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureFuseAES,
|
|
|
|
FeatureNEON,
|
|
|
|
FeatureFullFP16,
|
|
|
|
FeatureDotProd,
|
|
|
|
FeatureRCPC,
|
|
|
|
FeaturePerfMon
|
|
|
|
]>;
|
|
|
|
|
2017-10-18 05:46:15 +08:00
|
|
|
// Note that cyclone does not fuse AES instructions, but newer apple chips do
|
|
|
|
// perform the fusion and cyclone is used by default when targetting apple OSes.
|
2014-04-15 01:38:00 +08:00
|
|
|
def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
|
2016-06-03 02:03:53 +08:00
|
|
|
"Cyclone", [
|
|
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
2017-10-18 05:46:15 +08:00
|
|
|
FeatureArithmeticBccFusion,
|
|
|
|
FeatureArithmeticCbzFusion,
|
2014-04-15 01:38:00 +08:00
|
|
|
FeatureCrypto,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureDisableLatencySchedHeuristic,
|
|
|
|
FeatureFPARMv8,
|
2017-10-18 05:46:15 +08:00
|
|
|
FeatureFuseAES,
|
2018-09-20 04:50:51 +08:00
|
|
|
FeatureFuseCryptoEOR,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureNEON,
|
2015-09-02 00:23:45 +08:00
|
|
|
FeaturePerfMon,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureZCRegMove,
|
2017-12-18 18:36:00 +08:00
|
|
|
FeatureZCZeroing,
|
|
|
|
FeatureZCZeroingFPWorkaround
|
2016-06-03 02:03:53 +08:00
|
|
|
]>;
|
2014-04-15 01:38:00 +08:00
|
|
|
|
2016-01-05 20:51:59 +08:00
|
|
|
def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
|
2016-10-27 06:06:20 +08:00
|
|
|
"Samsung Exynos-M1 processors",
|
2017-01-25 01:34:31 +08:00
|
|
|
[FeatureSlowPaired128,
|
2016-10-27 06:06:20 +08:00
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
2018-01-30 23:40:22 +08:00
|
|
|
FeatureExynosCheapAsMoveHandling,
|
2018-10-26 00:45:46 +08:00
|
|
|
FeatureForce32BitJumpTables,
|
2017-02-01 10:54:39 +08:00
|
|
|
FeatureFuseAES,
|
2016-10-27 06:06:20 +08:00
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
2016-12-16 08:18:00 +08:00
|
|
|
FeatureSlowMisaligned128Store,
|
2016-10-27 06:06:20 +08:00
|
|
|
FeatureUseRSqrt,
|
2018-10-26 00:45:46 +08:00
|
|
|
FeatureZCZeroingFP]>;
|
2016-10-27 06:06:20 +08:00
|
|
|
|
|
|
|
def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
|
2018-01-23 03:03:26 +08:00
|
|
|
"Samsung Exynos-M2 processors",
|
2017-01-25 01:34:31 +08:00
|
|
|
[FeatureSlowPaired128,
|
2016-10-27 06:06:20 +08:00
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
2018-01-30 23:40:22 +08:00
|
|
|
FeatureExynosCheapAsMoveHandling,
|
2018-10-26 00:45:46 +08:00
|
|
|
FeatureForce32BitJumpTables,
|
2017-07-19 06:51:25 +08:00
|
|
|
FeatureFuseAES,
|
2016-10-27 06:06:20 +08:00
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
2016-12-16 08:18:00 +08:00
|
|
|
FeatureSlowMisaligned128Store,
|
2018-10-26 00:45:46 +08:00
|
|
|
FeatureZCZeroingFP]>;
|
2016-01-05 20:51:59 +08:00
|
|
|
|
2018-01-30 23:40:16 +08:00
|
|
|
def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
|
2018-01-23 03:03:26 +08:00
|
|
|
"Samsung Exynos-M3 processors",
|
|
|
|
[FeatureCRC,
|
|
|
|
FeatureCrypto,
|
2018-01-30 23:40:22 +08:00
|
|
|
FeatureExynosCheapAsMoveHandling,
|
2018-10-26 00:45:46 +08:00
|
|
|
FeatureForce32BitJumpTables,
|
2018-01-31 00:28:01 +08:00
|
|
|
FeatureFuseAddress,
|
2018-01-23 03:03:26 +08:00
|
|
|
FeatureFuseAES,
|
2018-02-24 03:27:43 +08:00
|
|
|
FeatureFuseCCSelect,
|
2018-01-23 03:03:26 +08:00
|
|
|
FeatureFuseLiterals,
|
2018-01-30 23:40:16 +08:00
|
|
|
FeatureLSLFast,
|
2018-01-23 03:03:26 +08:00
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
2018-01-30 23:40:16 +08:00
|
|
|
FeaturePredictableSelectIsExpensive,
|
2018-10-26 00:45:46 +08:00
|
|
|
FeatureZCZeroingFP]>;
|
2018-01-23 03:03:26 +08:00
|
|
|
|
2016-02-12 23:51:51 +08:00
|
|
|
def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
|
2016-06-03 02:03:53 +08:00
|
|
|
"Qualcomm Kryo processors", [
|
2016-02-12 23:51:51 +08:00
|
|
|
FeatureCRC,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureCrypto,
|
|
|
|
FeatureCustomCheapAsMoveHandling,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
2016-07-12 10:04:01 +08:00
|
|
|
FeaturePredictableSelectIsExpensive,
|
2017-04-01 02:16:53 +08:00
|
|
|
FeatureZCZeroing,
|
|
|
|
FeatureLSLFast
|
2016-06-03 02:03:53 +08:00
|
|
|
]>;
|
|
|
|
|
2016-11-16 05:34:12 +08:00
|
|
|
def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
|
|
|
|
"Qualcomm Falkor processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
2017-01-05 05:26:23 +08:00
|
|
|
FeatureCustomCheapAsMoveHandling,
|
2016-11-16 05:34:12 +08:00
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureNEON,
|
2017-01-05 05:26:23 +08:00
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
2017-01-17 00:28:43 +08:00
|
|
|
FeatureRDM,
|
2017-04-01 02:16:53 +08:00
|
|
|
FeatureZCZeroing,
|
2017-08-29 04:48:43 +08:00
|
|
|
FeatureLSLFast,
|
|
|
|
FeatureSlowSTRQro
|
2016-11-16 05:34:12 +08:00
|
|
|
]>;
|
|
|
|
|
2017-09-25 22:05:00 +08:00
|
|
|
def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
|
|
|
|
"Qualcomm Saphira processors", [
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureCustomCheapAsMoveHandling,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureNEON,
|
|
|
|
FeatureSPE,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
|
|
|
FeatureZCZeroing,
|
|
|
|
FeatureLSLFast,
|
2018-11-01 21:45:16 +08:00
|
|
|
HasV8_4aOps]>;
|
2017-09-25 22:05:00 +08:00
|
|
|
|
2017-03-08 03:42:40 +08:00
|
|
|
def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
|
|
|
|
"ThunderX2T99",
|
|
|
|
"Cavium ThunderX2 processors", [
|
2018-01-26 05:55:39 +08:00
|
|
|
FeatureAggressiveFMA,
|
2017-03-08 03:42:40 +08:00
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeatureArithmeticBccFusion,
|
|
|
|
FeatureNEON,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
|
|
|
FeatureLSE,
|
|
|
|
HasV8_1aOps]>;
|
2016-06-20 19:13:31 +08:00
|
|
|
|
2017-02-18 02:34:24 +08:00
|
|
|
def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
|
|
|
|
"Cavium ThunderX processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
|
|
|
FeatureNEON]>;
|
|
|
|
|
|
|
|
def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
|
|
|
|
"ThunderXT88",
|
|
|
|
"Cavium ThunderX processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
|
|
|
FeatureNEON]>;
|
|
|
|
|
|
|
|
def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
|
|
|
|
"ThunderXT81",
|
|
|
|
"Cavium ThunderX processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
|
|
|
FeatureNEON]>;
|
|
|
|
|
|
|
|
def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
|
|
|
|
"ThunderXT83",
|
|
|
|
"Cavium ThunderX processors", [
|
|
|
|
FeatureCRC,
|
|
|
|
FeatureCrypto,
|
|
|
|
FeatureFPARMv8,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler,
|
|
|
|
FeaturePredictableSelectIsExpensive,
|
|
|
|
FeatureNEON]>;
|
|
|
|
|
2016-06-03 02:03:53 +08:00
|
|
|
def : ProcessorModel<"generic", NoSchedModel, [
|
|
|
|
FeatureFPARMv8,
|
[AArch64] Enable FeatureFuseAES for the generic processor model.
Summary:
Scheduling AESE/AESMC and AESD/AESIMC instruction pairs back-to-back
gives a double digit speedup on benchmarks using those instructions on
Cortex-A processors. In GCC, this optimization is part of the generic
processor model as well.
This change should not have a major performance impact on processors
that do not optimize AES instruction pairs, although I only had access
to Cortex-A processors for benchmarking.
Reviewers: rengolin, kristof.beyls, javed.absar, evandro, silviu.baranga, MatzeB, mcrosier, joelkevinjones, joel_k_jones, bmakam, t.p.northover
Reviewed By: evandro
Subscribers: sbaranga, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D33836
llvm-svn: 305457
2017-06-15 17:31:23 +08:00
|
|
|
FeatureFuseAES,
|
2016-06-03 02:03:53 +08:00
|
|
|
FeatureNEON,
|
|
|
|
FeaturePerfMon,
|
|
|
|
FeaturePostRAScheduler
|
|
|
|
]>;
|
2014-04-15 01:38:00 +08:00
|
|
|
|
2017-08-21 16:43:06 +08:00
|
|
|
// FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
|
2015-12-02 19:53:44 +08:00
|
|
|
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
|
2014-04-19 05:22:04 +08:00
|
|
|
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
|
2017-08-21 16:43:06 +08:00
|
|
|
def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
|
2014-06-12 05:06:56 +08:00
|
|
|
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
|
2017-08-21 16:43:06 +08:00
|
|
|
// FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57.
|
[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
llvm-svn: 273277
2016-06-21 23:53:54 +08:00
|
|
|
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
|
|
|
|
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
|
2017-08-21 16:43:06 +08:00
|
|
|
def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
|
2014-04-15 01:38:00 +08:00
|
|
|
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
|
2016-02-06 08:01:41 +08:00
|
|
|
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
|
2016-10-27 06:06:20 +08:00
|
|
|
def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
|
2018-01-30 23:40:16 +08:00
|
|
|
def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
|
2018-06-07 02:56:00 +08:00
|
|
|
def : ProcessorModel<"exynos-m4", ExynosM3Model, [ProcExynosM3]>;
|
2016-11-30 04:00:27 +08:00
|
|
|
def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
|
2017-09-25 22:05:00 +08:00
|
|
|
def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
|
2016-02-12 23:51:51 +08:00
|
|
|
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
|
2017-02-18 02:34:24 +08:00
|
|
|
// Cavium ThunderX/ThunderX T8X Processors
|
|
|
|
def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
|
|
|
|
def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
|
|
|
|
def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
|
|
|
|
def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
|
2017-03-08 03:42:40 +08:00
|
|
|
// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
|
|
|
|
def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Assembly parser
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
def GenericAsmParserVariant : AsmParserVariant {
|
|
|
|
int Variant = 0;
|
|
|
|
string Name = "generic";
|
2015-11-09 08:31:07 +08:00
|
|
|
string BreakCharacters = ".";
|
[AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands
Summary:
Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand.
Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, MatzeB, t.p.northover
Reviewed By: fhahn
Subscribers: t.p.northover, MatzeB, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D41442
llvm-svn: 322070
2018-01-09 19:17:06 +08:00
|
|
|
string TokenizingCharacters = "[]*!/";
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
def AppleAsmParserVariant : AsmParserVariant {
|
|
|
|
int Variant = 1;
|
|
|
|
string Name = "apple-neon";
|
2015-11-09 08:31:07 +08:00
|
|
|
string BreakCharacters = ".";
|
[AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands
Summary:
Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand.
Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, MatzeB, t.p.northover
Reviewed By: fhahn
Subscribers: t.p.northover, MatzeB, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D41442
llvm-svn: 322070
2018-01-09 19:17:06 +08:00
|
|
|
string TokenizingCharacters = "[]*!/";
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Assembly printer
|
|
|
|
//===----------------------------------------------------------------------===//
|
2014-05-24 20:50:23 +08:00
|
|
|
// AArch64 Uses the MC printer for asm output, so make sure the TableGen
|
2014-03-29 18:18:08 +08:00
|
|
|
// AsmWriter bits get associated with the correct class.
|
|
|
|
def GenericAsmWriter : AsmWriter {
|
|
|
|
string AsmWriterClassName = "InstPrinter";
|
2015-03-28 04:36:02 +08:00
|
|
|
int PassSubtarget = 1;
|
2014-03-29 18:18:08 +08:00
|
|
|
int Variant = 0;
|
|
|
|
bit isMCAsmWriter = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
def AppleAsmWriter : AsmWriter {
|
|
|
|
let AsmWriterClassName = "AppleInstPrinter";
|
2015-03-28 04:36:02 +08:00
|
|
|
int PassSubtarget = 1;
|
2014-03-29 18:18:08 +08:00
|
|
|
int Variant = 1;
|
|
|
|
int isMCAsmWriter = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Target Declaration
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
def AArch64 : Target {
|
|
|
|
let InstructionSet = AArch64InstrInfo;
|
2014-03-29 18:18:08 +08:00
|
|
|
let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
|
|
|
|
let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
|
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
llvm-svn: 325931
2018-02-24 02:25:08 +08:00
|
|
|
let AllowRegisterRenaming = 1;
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
2018-11-09 21:15:32 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Pfm Counters
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
include "AArch64PfmCounters.td"
|