llvm-project/llvm/test/CodeGen/X86/widen_cast-5.ll

; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: movl
; CHECK: movq

; bitcast a i64 to v2i32
define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {
entry:
	%conv = bitcast i64 %src to <2 x i32>
	%xor = xor <2 x i32> %conv, < i32 255, i32 32767 >
	store <2 x i32> %xor, <2 x i32>* %dst.addr
	ret void
}
Update tests to use sse4.2 instead of sse42. llvm-svn: 189145 2013-08-24 04:46:35 +08:00			`; RUN: llc < %s -march=x86 -mattr=+sse4.2 \| FileCheck %s`
Update tests to use FileCheck llvm-svn: 84282 2009-10-17 06:09:05 +08:00			`; CHECK: movl`
[X86] add an exedepfix entry for movq == movlps == movlpd This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 llvm-svn: 235014 2015-04-15 23:47:51 +08:00			`; CHECK: movq`
Added some basic test cases for r61209 llvm-svn: 61210 2008-12-19 04:05:58 +08:00
			`; bitcast a i64 to v2i32`
			`define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {`
			`entry:`
			`%conv = bitcast i64 %src to <2 x i32>`
			`%xor = xor <2 x i32> %conv, < i32 255, i32 32767 >`
			`store <2 x i32> %xor, <2 x i32>* %dst.addr`
			`ret void`
			`}`