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llvm-project/llvm/test/CodeGen/Thumb2/tpsoft.ll

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ARM: Fix TPsoft for Thumb mode Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
2014-06-24 23:45:59 +08:00
; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -filetype=obj -o - | \
; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ -check-prefix=ELFOBJ-LE %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -filetype=obj -o - | \
; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ -check-prefix=ELFOBJ-BE %s
;; Make sure that bl __aeabi_read_tp is materialized and fixed up correctly
;; in the obj case.
@i = external thread_local global i32
@a = external global i8
@b = external global [10 x i8]
define arm_aapcs_vfpcc i32 @main() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @i, align 4
ARM: Fix TPsoft for Thumb mode Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
2014-06-24 23:45:59 +08:00
switch i32 %0, label %bb2 [
i32 12, label %bb
i32 13, label %bb1
]
bb: ; preds = %entry
%1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
ret i32 %1
; ELFASM: bl __aeabi_read_tp
; ELFOBJ: Sections [
; ELFOBJ: Section {
; ELFOBJ: Name: .text
; ELFOBJ-LE: SectionData (
ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. This makes it more likely that we can use the 16-bit push and pop instructions on Thumb-2, saving around 4 bytes per function. Differential Revision: http://reviews.llvm.org/D9165 llvm-svn: 235637
2015-04-24 04:31:26 +08:00
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580D28
ARM: Fix TPsoft for Thumb mode Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
2014-06-24 23:45:59 +08:00
; ELFOBJ-BE: SectionData (
ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. This makes it more likely that we can use the 16-bit push and pop instructions on Thumb-2, saving around 4 bytes per function. Differential Revision: http://reviews.llvm.org/D9165 llvm-svn: 235637
2015-04-24 04:31:26 +08:00
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280D
ARM: Fix TPsoft for Thumb mode Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
2014-06-24 23:45:59 +08:00
bb1: ; preds = %entry
%2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
ret i32 %2
bb2: ; preds = %entry
ret i32 -1
}
declare arm_aapcs_vfpcc i32 @foo(i8*)
declare arm_aapcs_vfpcc i32 @bar(i32*)