2012-05-05 04:18:50 +08:00
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//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXTargetMachine.h"
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#include "MCTargetDesc/NVPTXMCAsmInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "NVPTX.h"
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2012-05-05 04:18:50 +08:00
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#include "NVPTXAllocaHoisting.h"
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2012-12-04 00:50:05 +08:00
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#include "NVPTXLowerAggrCopies.h"
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2014-11-13 17:26:31 +08:00
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#include "NVPTXTargetObjectFile.h"
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2015-01-31 19:17:59 +08:00
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#include "NVPTXTargetTransformInfo.h"
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2012-05-05 04:18:50 +08:00
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#include "llvm/Analysis/Passes.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/DataLayout.h"
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2014-01-12 19:10:32 +08:00
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#include "llvm/IR/IRPrintingPasses.h"
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2015-02-13 18:01:29 +08:00
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#include "llvm/IR/LegacyPassManager.h"
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2014-01-13 17:26:24 +08:00
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#include "llvm/IR/Verifier.h"
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2012-05-05 04:18:50 +08:00
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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2012-05-05 04:18:50 +08:00
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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2016-03-11 16:50:55 +08:00
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#include "llvm/Transforms/Scalar/GVN.h"
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2012-05-05 04:18:50 +08:00
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using namespace llvm;
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2016-03-21 04:59:20 +08:00
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static cl::opt<bool> UseInferAddressSpaces(
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"nvptx-use-infer-addrspace", cl::init(false), cl::Hidden,
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cl::desc("Optimize address spaces using NVPTXInferAddressSpaces instead of "
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"NVPTXFavorNonGenericAddrSpaces"));
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2013-03-30 22:29:25 +08:00
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namespace llvm {
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void initializeNVVMReflectPass(PassRegistry&);
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2013-05-20 20:13:32 +08:00
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void initializeGenericToNVVMPass(PassRegistry&);
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2015-03-11 03:20:52 +08:00
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void initializeNVPTXAllocaHoistingPass(PassRegistry &);
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2014-03-31 23:56:26 +08:00
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void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
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2014-04-04 05:18:25 +08:00
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void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
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2016-03-21 04:59:20 +08:00
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void initializeNVPTXInferAddressSpacesPass(PassRegistry &);
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2015-07-17 00:27:19 +08:00
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void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
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2015-06-05 05:28:26 +08:00
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void initializeNVPTXLowerKernelArgsPass(PassRegistry &);
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2015-06-18 06:31:02 +08:00
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void initializeNVPTXLowerAllocaPass(PassRegistry &);
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2013-03-30 22:29:25 +08:00
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}
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2012-05-05 04:18:50 +08:00
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extern "C" void LLVMInitializeNVPTXTarget() {
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// Register the target.
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RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
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RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
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2013-03-30 22:29:25 +08:00
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// FIXME: This pass is really intended to be invoked during IR optimization,
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// but it's very NVPTX-specific.
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2015-07-17 00:27:19 +08:00
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeNVVMReflectPass(PR);
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initializeGenericToNVVMPass(PR);
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initializeNVPTXAllocaHoistingPass(PR);
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initializeNVPTXAssignValidGlobalNamesPass(PR);
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initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
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2016-03-21 04:59:20 +08:00
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initializeNVPTXInferAddressSpacesPass(PR);
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2015-07-17 00:27:19 +08:00
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initializeNVPTXLowerKernelArgsPass(PR);
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initializeNVPTXLowerAllocaPass(PR);
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initializeNVPTXLowerAggrCopiesPass(PR);
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2012-05-05 04:18:50 +08:00
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}
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2015-01-27 03:03:15 +08:00
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static std::string computeDataLayout(bool is64Bit) {
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std::string Ret = "e";
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if (!is64Bit)
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Ret += "-p:32:32";
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Ret += "-i64:64-v16:16-v32:32-n16:32:64";
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return Ret;
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}
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2015-06-12 03:41:26 +08:00
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NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
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2014-06-27 09:27:06 +08:00
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64bit)
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2015-03-12 08:07:24 +08:00
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: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
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CM, OL),
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is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
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2015-06-12 03:41:26 +08:00
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Subtarget(TT, CPU, FS, *this) {
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if (TT.getOS() == Triple::NVCL)
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2015-02-19 08:08:14 +08:00
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drvInterface = NVPTX::NVCL;
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else
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drvInterface = NVPTX::CUDA;
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2013-05-13 09:16:13 +08:00
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initAsmInfo();
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}
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2012-05-05 04:18:50 +08:00
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2014-11-21 07:37:18 +08:00
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NVPTXTargetMachine::~NVPTXTargetMachine() {}
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2012-05-05 04:18:50 +08:00
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void NVPTXTargetMachine32::anchor() {}
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2015-06-12 03:41:26 +08:00
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NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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2013-03-30 22:29:21 +08:00
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: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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2012-05-05 04:18:50 +08:00
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void NVPTXTargetMachine64::anchor() {}
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2015-06-12 03:41:26 +08:00
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NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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2013-03-30 22:29:21 +08:00
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: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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2012-05-05 04:18:50 +08:00
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2013-05-24 01:10:37 +08:00
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namespace {
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2012-05-05 04:18:50 +08:00
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class NVPTXPassConfig : public TargetPassConfig {
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public:
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NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
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2013-03-30 22:29:21 +08:00
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: TargetPassConfig(TM, PM) {}
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2012-05-05 04:18:50 +08:00
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NVPTXTargetMachine &getNVPTXTargetMachine() const {
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return getTM<NVPTXTargetMachine>();
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}
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2014-04-29 15:57:44 +08:00
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void addIRPasses() override;
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bool addInstSelector() override;
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2014-12-12 05:26:47 +08:00
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void addPostRegAlloc() override;
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2014-06-28 02:35:14 +08:00
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void addMachineSSAOptimization() override;
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2014-04-29 15:57:44 +08:00
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FunctionPass *createTargetRegisterAllocator(bool) override;
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void addFastRegAlloc(FunctionPass *RegAllocPass) override;
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void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
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2015-07-23 12:59:07 +08:00
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private:
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2016-02-04 12:15:36 +08:00
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// If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
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// function is only called in opt mode.
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2015-07-23 12:59:07 +08:00
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void addEarlyCSEOrGVNPass();
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2016-02-04 12:15:36 +08:00
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// Add passes that propagate special memory spaces.
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2016-03-21 04:59:20 +08:00
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void addAddressSpaceInferencePasses();
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2016-02-04 12:15:36 +08:00
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// Add passes that perform straight-line scalar optimizations.
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void addStraightLineScalarOptimizationPasses();
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2012-05-05 04:18:50 +08:00
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};
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2013-05-24 01:10:37 +08:00
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} // end anonymous namespace
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2012-05-05 04:18:50 +08:00
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TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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2016-02-04 12:15:36 +08:00
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return new NVPTXPassConfig(this, PM);
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2012-05-05 04:18:50 +08:00
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}
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2015-02-01 21:20:00 +08:00
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TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
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2015-09-17 07:38:13 +08:00
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return TargetIRAnalysis([this](const Function &F) {
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2015-07-09 10:08:42 +08:00
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return TargetTransformInfo(NVPTXTTIImpl(this, F));
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});
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2014-11-11 02:38:25 +08:00
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}
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2015-07-23 12:59:07 +08:00
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void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
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if (getOptLevel() == CodeGenOpt::Aggressive)
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addPass(createGVNPass());
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else
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addPass(createEarlyCSEPass());
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}
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2016-03-21 04:59:20 +08:00
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void NVPTXPassConfig::addAddressSpaceInferencePasses() {
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2015-06-05 05:28:26 +08:00
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addPass(createNVPTXLowerKernelArgsPass(&getNVPTXTargetMachine()));
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2015-06-09 08:05:56 +08:00
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// NVPTXLowerKernelArgs emits alloca for byval parameters which can often
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2015-06-18 06:31:02 +08:00
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// be eliminated by SROA.
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2015-06-09 08:05:56 +08:00
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addPass(createSROAPass());
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2015-06-18 06:31:02 +08:00
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addPass(createNVPTXLowerAllocaPass());
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2016-03-21 04:59:20 +08:00
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if (UseInferAddressSpaces) {
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addPass(createNVPTXInferAddressSpacesPass());
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} else {
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addPass(createNVPTXFavorNonGenericAddrSpacesPass());
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// FavorNonGenericAddrSpaces shortcuts unnecessary addrspacecasts, and leave
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// them unused. We could remove dead code in an ad-hoc manner, but that
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// requires manual work and might be error-prone.
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addPass(createDeadCodeEliminationPass());
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}
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2016-02-04 12:15:36 +08:00
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}
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2015-07-23 12:59:07 +08:00
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2016-02-04 12:15:36 +08:00
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void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
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2014-05-02 02:38:36 +08:00
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addPass(createSeparateConstOffsetFromGEPPass());
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2015-07-17 04:13:48 +08:00
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addPass(createSpeculativeExecutionPass());
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2015-04-24 04:00:04 +08:00
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// ReassociateGEPs exposes more opportunites for SLSR. See
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// the example in reassociate-geps-and-slsr.ll.
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addPass(createStraightLineStrengthReducePass());
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// SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
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// EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
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// for some of our benchmarks.
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2015-07-23 12:59:07 +08:00
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addEarlyCSEOrGVNPass();
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2015-04-24 12:22:39 +08:00
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// Run NaryReassociate after EarlyCSE/GVN to be more effective.
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addPass(createNaryReassociatePass());
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2015-05-28 12:56:52 +08:00
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// NaryReassociate on GEPs creates redundant common expressions, so run
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// EarlyCSE after it.
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addPass(createEarlyCSEPass());
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2016-02-04 12:15:36 +08:00
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}
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void NVPTXPassConfig::addIRPasses() {
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// The following passes are known to not play well with virtual regs hanging
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// around after register allocation (which in our case, is *all* registers).
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// We explicitly disable them here. We do, however, need some functionality
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// of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
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// NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
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disablePass(&PrologEpilogCodeInserterID);
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disablePass(&MachineCopyPropagationID);
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disablePass(&TailDuplicateID);
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2016-03-29 01:05:30 +08:00
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disablePass(&StackMapLivenessID);
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disablePass(&LiveDebugValuesID);
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disablePass(&PostRASchedulerID);
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disablePass(&FuncletLayoutID);
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2016-02-04 12:15:36 +08:00
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addPass(createNVVMReflectPass());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createNVPTXImageOptimizerPass());
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addPass(createNVPTXAssignValidGlobalNamesPass());
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addPass(createGenericToNVVMPass());
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if (getOptLevel() != CodeGenOpt::None) {
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2016-03-21 04:59:20 +08:00
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addAddressSpaceInferencePasses();
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2016-02-04 12:15:36 +08:00
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addStraightLineScalarOptimizationPasses();
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}
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2015-07-23 12:59:07 +08:00
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// === LSR and other generic IR passes ===
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TargetPassConfig::addIRPasses();
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// EarlyCSE is not always strong enough to clean up what LSR produces. For
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// example, GVN can combine
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//
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// %0 = add %a, %b
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// %1 = add %b, %a
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//
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// and
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//
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// %0 = shl nsw %a, 2
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// %1 = shl %a, 2
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//
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// but EarlyCSE can do neither of them.
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2016-02-04 12:15:36 +08:00
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if (getOptLevel() != CodeGenOpt::None)
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addEarlyCSEOrGVNPass();
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2013-05-20 20:13:32 +08:00
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}
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2012-05-05 04:18:50 +08:00
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bool NVPTXPassConfig::addInstSelector() {
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2015-03-21 11:13:03 +08:00
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const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
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2014-04-09 23:39:15 +08:00
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2012-07-03 03:48:31 +08:00
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addPass(createLowerAggrCopies());
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addPass(createAllocaHoisting());
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addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
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2014-04-09 23:39:15 +08:00
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if (!ST.hasImageHandles())
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addPass(createNVPTXReplaceImageHandlesPass());
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2012-05-05 04:18:50 +08:00
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return false;
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}
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2014-12-12 05:26:47 +08:00
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void NVPTXPassConfig::addPostRegAlloc() {
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addPass(createNVPTXPrologEpilogPass(), false);
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2015-07-02 04:08:06 +08:00
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// NVPTXPrologEpilogPass calculates frame object offset and replace frame
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// index with VRFrame register. NVPTXPeephole need to be run after that and
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// will replace VRFrame with VRFrameLocal when possible.
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|
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addPass(createNVPTXPeephole());
|
2013-05-31 20:14:49 +08:00
|
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|
}
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|
2013-06-01 03:21:58 +08:00
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|
|
FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
|
2014-04-25 13:30:21 +08:00
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|
|
return nullptr; // No reg alloc
|
2013-06-01 03:21:58 +08:00
|
|
|
}
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|
|
|
|
2013-05-31 20:14:49 +08:00
|
|
|
void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
|
2013-06-01 03:21:58 +08:00
|
|
|
assert(!RegAllocPass && "NVPTX uses no regalloc!");
|
2013-10-11 20:39:39 +08:00
|
|
|
addPass(&PHIEliminationID);
|
|
|
|
addPass(&TwoAddressInstructionPassID);
|
2013-05-31 20:14:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
|
2013-06-01 03:21:58 +08:00
|
|
|
assert(!RegAllocPass && "NVPTX uses no regalloc!");
|
2013-10-11 20:39:39 +08:00
|
|
|
|
|
|
|
addPass(&ProcessImplicitDefsID);
|
|
|
|
addPass(&LiveVariablesID);
|
|
|
|
addPass(&MachineLoopInfoID);
|
|
|
|
addPass(&PHIEliminationID);
|
|
|
|
|
|
|
|
addPass(&TwoAddressInstructionPassID);
|
|
|
|
addPass(&RegisterCoalescerID);
|
|
|
|
|
|
|
|
// PreRA instruction scheduling.
|
|
|
|
if (addPass(&MachineSchedulerID))
|
|
|
|
printAndVerify("After Machine Scheduling");
|
|
|
|
|
|
|
|
|
|
|
|
addPass(&StackSlotColoringID);
|
|
|
|
|
|
|
|
// FIXME: Needs physical registers
|
|
|
|
//addPass(&PostRAMachineLICMID);
|
|
|
|
|
|
|
|
printAndVerify("After StackSlotColoring");
|
2013-05-31 20:14:49 +08:00
|
|
|
}
|
2014-06-28 02:35:14 +08:00
|
|
|
|
|
|
|
void NVPTXPassConfig::addMachineSSAOptimization() {
|
|
|
|
// Pre-ra tail duplication.
|
|
|
|
if (addPass(&EarlyTailDuplicateID))
|
|
|
|
printAndVerify("After Pre-RegAlloc TailDuplicate");
|
|
|
|
|
|
|
|
// Optimize PHIs before DCE: removing dead PHI cycles may make more
|
|
|
|
// instructions dead.
|
|
|
|
addPass(&OptimizePHIsID);
|
|
|
|
|
|
|
|
// This pass merges large allocas. StackSlotColoring is a different pass
|
|
|
|
// which merges spill slots.
|
|
|
|
addPass(&StackColoringID);
|
|
|
|
|
|
|
|
// If the target requests it, assign local variables to stack slots relative
|
|
|
|
// to one another and simplify frame index references where possible.
|
|
|
|
addPass(&LocalStackSlotAllocationID);
|
|
|
|
|
|
|
|
// With optimization, dead code should already be eliminated. However
|
|
|
|
// there is one known exception: lowered code for arguments that are only
|
|
|
|
// used by tail calls, where the tail calls reuse the incoming stack
|
|
|
|
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
|
|
|
|
addPass(&DeadMachineInstructionElimID);
|
|
|
|
printAndVerify("After codegen DCE pass");
|
|
|
|
|
|
|
|
// Allow targets to insert passes that improve instruction level parallelism,
|
|
|
|
// like if-conversion. Such passes will typically need dominator trees and
|
|
|
|
// loop info, just like LICM and CSE below.
|
|
|
|
if (addILPOpts())
|
|
|
|
printAndVerify("After ILP optimizations");
|
|
|
|
|
|
|
|
addPass(&MachineLICMID);
|
|
|
|
addPass(&MachineCSEID);
|
|
|
|
|
|
|
|
addPass(&MachineSinkingID);
|
|
|
|
printAndVerify("After Machine LICM, CSE and Sinking passes");
|
|
|
|
|
|
|
|
addPass(&PeepholeOptimizerID);
|
|
|
|
printAndVerify("After codegen peephole optimization pass");
|
|
|
|
}
|