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llvm-project/llvm/lib/Target/Hexagon/HexagonFrameLowering.h

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Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
//=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
Canonicalize header guards into a common format. Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
2014-08-14 00:26:38 +08:00
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
Hexagon backend support llvm-svn: 146412
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#include "Hexagon.h"
[Hexagon] Optimize stack slot spills Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
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#include "HexagonBlockRanges.h"
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#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
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class HexagonInstrInfo;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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class HexagonRegisterInfo;
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
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Hexagon backend support llvm-svn: 146412
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class HexagonFrameLowering : public TargetFrameLowering {
public:
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
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explicit HexagonFrameLowering()
: TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {}
Hexagon backend support llvm-svn: 146412
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[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
2015-04-24 00:05:39 +08:00
// All of the prolog/epilog functionality, including saving and restoring
// callee-saved registers is handled in emitPrologue. This is to have the
// logic for shrink-wrapping in one place.
[ShrinkWrap] Add (a simplified version) of shrink-wrapping. This patch introduces a new pass that computes the safe point to insert the prologue and epilogue of the function. The interest is to find safe points that are cheaper than the entry and exits blocks. As an example and to avoid regressions to be introduce, this patch also implements the required bits to enable the shrink-wrapping pass for AArch64. ** Context ** Currently we insert the prologue and epilogue of the method/function in the entry and exits blocks. Although this is correct, we can do a better job when those are not immediately required and insert them at less frequently executed places. The job of the shrink-wrapping pass is to identify such places. ** Motivating example ** Let us consider the following function that perform a call only in one branch of a if: define i32 @f(i32 %a, i32 %b) { %tmp = alloca i32, align 4 %tmp2 = icmp slt i32 %a, %b br i1 %tmp2, label %true, label %false true: store i32 %a, i32* %tmp, align 4 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) br label %false false: %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] ret i32 %tmp.0 } On AArch64 this code generates (removing the cfi directives to ease readabilities): _f: ; @f ; BB#0: stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething LBB0_2: ; %false mov sp, x29 ldp x29, x30, [sp], #16 ret With shrink-wrapping we could generate: _f: ; @f ; BB#0: cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething add sp, x29, #16 ; =16 ldp x29, x30, [sp], #16 LBB0_2: ; %false ret Therefore, we would pay the overhead of setting up/destroying the frame only if we actually do the call. ** Proposed Solution ** This patch introduces a new machine pass that perform the shrink-wrapping analysis (See the comments at the beginning of ShrinkWrap.cpp for more details). It then stores the safe save and restore point into the MachineFrameInfo attached to the MachineFunction. This information is then used by the PrologEpilogInserter (PEI) to place the related code at the right place. This pass runs right before the PEI. Unlike the original paper of Chow from PLDI’88, this implementation of shrink-wrapping does not use expensive data-flow analysis and does not need hack to properly avoid frequently executed point. Instead, it relies on dominance and loop properties. The pass is off by default and each target can opt-in by setting the EnableShrinkWrap boolean to true in their derived class of TargetPassConfig. This setting can also be overwritten on the command line by using -enable-shrink-wrap. Before you try out the pass for your target, make sure you properly fix your emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not necessarily the entry block. ** Design Decisions ** 1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but for debugging and clarity I thought it was best to have its own file. 2. Right now, we only support one save point and one restore point. At some point we can expand this to several save point and restore point, the impacted component would then be: - The pass itself: New algorithm needed. - MachineFrameInfo: Hold a list or set of Save/Restore point instead of one pointer. - PEI: Should loop over the save point and restore point. Anyhow, at least for this first iteration, I do not believe this is interesting to support the complex cases. We should revisit that when we motivating examples. Differential Revision: http://reviews.llvm.org/D9210 <rdar://problem/3201744> llvm-svn: 236507
2015-05-06 01:38:16 +08:00
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
override;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
override {}
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const override {
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
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return true;
}
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const override {
return true;
}
Change eliminateCallFramePseudoInstr() to return an iterator This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
2016-04-01 02:33:38 +08:00
MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
2015-04-23 00:43:53 +08:00
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
[Hexagon] Replace expansion of spill pseudo-instructions in frame lowering Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
2016-02-13 02:19:53 +08:00
RegScavenger *RS = nullptr) const override;
PrologEpilogInserter: Rewrite API to determine callee save regsiters. This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 llvm-svn: 242165
2015-07-15 01:17:13 +08:00
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
[Hexagon] Replace expansion of spill pseudo-instructions in frame lowering Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
2016-02-13 02:19:53 +08:00
RegScavenger *RS) const override;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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bool targetHandlesStackFrameRounding() const override {
return true;
}
Remove redundant TargetFrameLowering::getFrameIndexOffset virtual function. This was the same as getFrameIndexReference, but without the FrameReg output. Differential Revision: http://reviews.llvm.org/D12042 llvm-svn: 245148
2015-08-15 10:32:35 +08:00
int getFrameIndexReference(const MachineFunction &MF, int FI,
[Hexagon] Replace expansion of spill pseudo-instructions in frame lowering Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
2016-02-13 02:19:53 +08:00
unsigned &FrameReg) const override;
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
bool hasFP(const MachineFunction &MF) const override;
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
2015-04-23 00:43:53 +08:00
const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
[Hexagon] Replace expansion of spill pseudo-instructions in frame lowering Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
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const override {
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
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static const SpillSlot Offsets[] = {
{ Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
{ Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
{ Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
{ Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
{ Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
{ Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
};
NumEntries = array_lengthof(Offsets);
return Offsets;
}
bool assignCalleeSavedSpillSlots(MachineFunction &MF,
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
const override;
[Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
2015-04-23 00:43:53 +08:00
bool needsAligna(const MachineFunction &MF) const;
[Hexagon] Fix debug information for local objects - Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
2015-10-20 02:30:27 +08:00
const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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[Hexagon] Delay emission of CFI instructions Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
2015-10-20 01:46:01 +08:00
void insertCFIInstructions(MachineFunction &MF) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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private:
typedef std::vector<CalleeSavedInfo> CSIVect;
void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
unsigned SP, unsigned CF) const;
[Hexagon] Add support for run-time stack overflow checking Patch by Sundeep Kushwaha. llvm-svn: 264328
2016-03-25 04:20:07 +08:00
void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
[Hexagon] Add support for run-time stack overflow checking Patch by Sundeep Kushwaha. llvm-svn: 264328
2016-03-25 04:20:07 +08:00
const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
const HexagonRegisterInfo &HRI) const;
[Hexagon] Add saved callee-saved registers as live-in in non-wrapped blocks The callee-saved registers that are saved in a function are not pristine, and so they can be defined and used. In case of shrink-wrapping though, there are blocks that are outside of the save/restore range, and in those blocks the saved registers must be treated as pristine. To avoid any uses of these registers, add them as live-in in all those blocks. This was already done for blocks reaching function exits after restore, add code that does the same for blocks reached from the function entry before save. llvm-svn: 276886
2016-07-28 00:26:39 +08:00
void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
[Hexagon] Enable the post-RA scheduler The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
2016-05-27 03:44:28 +08:00
BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
[Hexagon] Delay emission of CFI instructions Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
2015-10-20 01:46:01 +08:00
void insertCFIInstructionsAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator At) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
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void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
[Hexagon] Replace expansion of spill pseudo-instructions in frame lowering Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
2016-02-13 02:19:53 +08:00
bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
SmallVectorImpl<unsigned> &NewRegs) const;
bool expandSpillMacros(MachineFunction &MF,
SmallVectorImpl<unsigned> &NewRegs) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
2015-04-24 00:05:39 +08:00
[Hexagon] Optimize stack slot spills Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
2016-02-13 06:53:35 +08:00
unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
HexagonBlockRanges::InstrIndexMap &IndexMap,
HexagonBlockRanges::RegToRangeMap &DeadMap,
const TargetRegisterClass *RC) const;
void optimizeSpillSlots(MachineFunction &MF,
SmallVectorImpl<unsigned> &VRegs) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
2015-04-24 00:05:39 +08:00
void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
MachineBasicBlock *&EpilogB) const;
[Hexagon] Register save/restore functions do not follow regular conventions Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
2016-04-26 01:49:44 +08:00
void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
bool IsDef, bool IsKill) const;
[Hexagon] Check for offset overflow when reserving scavenging slots Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
2016-08-02 01:15:30 +08:00
bool shouldInlineCSR(MachineFunction &MF, const CSIVect &CSI) const;
[Hexagon] Shrink-wrap stack frame (Hexagon-specific) llvm-svn: 235603
2015-04-24 00:05:39 +08:00
bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const;
bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
[Hexagon] Check for offset overflow when reserving scavenging slots Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
2016-08-02 01:15:30 +08:00
bool mayOverflowFrameOffset(MachineFunction &MF) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
};
Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) Apparently, the style needs to be agreed upon first. llvm-svn: 240390
2015-06-23 17:49:53 +08:00
} // End llvm namespace
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
#endif