llvm-project/llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xorl

define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
entry:
	tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
	ret i32 %0
}

declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802 2016-07-08 06:50:23 +08:00			`; RUN: llc < %s -mtriple=x86_64-apple-darwin \| grep xorl`
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman. llvm-svn: 54903 2008-08-18 03:22:34 +08:00
			`define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {`
			`entry:`
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498 2011-04-14 09:46:37 +08:00			`tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone`
			`ret i32 %0`
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman. llvm-svn: 54903 2008-08-18 03:22:34 +08:00			`}`

			`declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone`