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llvm-project/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll

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Add a new pass on machine instructions to optimize away PHI cycles that reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
2010-02-12 09:30:21 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define i32 @test(i32 %n) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test:
Add a new pass on machine instructions to optimize away PHI cycles that reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
2010-02-12 09:30:21 +08:00
; CHECK-NOT: mov
; CHECK: return
entry:
%0 = icmp eq i32 %n, 1 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
bb.nph: ; preds = %entry
%tmp = add i32 %n, -1 ; <i32> [#uses=1]
br label %bb
bb: ; preds = %bb.nph, %bb
%indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=1]
%u.05 = phi i64 [ undef, %bb.nph ], [ %ins, %bb ] ; <i64> [#uses=1]
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%1 = tail call i32 @f() nounwind ; <i32> [#uses=1]
Add a new pass on machine instructions to optimize away PHI cycles that reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
2010-02-12 09:30:21 +08:00
%tmp4 = zext i32 %1 to i64 ; <i64> [#uses=1]
%mask = and i64 %u.05, -4294967296 ; <i64> [#uses=1]
%ins = or i64 %tmp4, %mask ; <i64> [#uses=2]
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
tail call void @g(i64 %ins) nounwind
Add a new pass on machine instructions to optimize away PHI cycles that reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
2010-02-12 09:30:21 +08:00
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %indvar.next, %tmp ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry
ret i32 undef
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define i32 @test_dead_cycle(i32 %n) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test_dead_cycle:
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK: bl
Besides removing phi cycles that reduce to a single value, also remove dead phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
2010-02-13 08:31:44 +08:00
; CHECK-NOT: mov
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK: bl
Besides removing phi cycles that reduce to a single value, also remove dead phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
2010-02-13 08:31:44 +08:00
entry:
%0 = icmp eq i32 %n, 1 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
bb.nph: ; preds = %entry
%tmp = add i32 %n, -1 ; <i32> [#uses=2]
br label %bb
bb: ; preds = %bb.nph, %bb2
%indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb2 ] ; <i32> [#uses=2]
%u.17 = phi i64 [ undef, %bb.nph ], [ %u.0, %bb2 ] ; <i64> [#uses=2]
%tmp9 = sub i32 %tmp, %indvar ; <i32> [#uses=1]
%1 = icmp sgt i32 %tmp9, 1 ; <i1> [#uses=1]
br i1 %1, label %bb1, label %bb2
bb1: ; preds = %bb
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%2 = tail call i32 @f() nounwind ; <i32> [#uses=1]
Besides removing phi cycles that reduce to a single value, also remove dead phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
2010-02-13 08:31:44 +08:00
%tmp6 = zext i32 %2 to i64 ; <i64> [#uses=1]
%mask = and i64 %u.17, -4294967296 ; <i64> [#uses=1]
%ins = or i64 %tmp6, %mask ; <i64> [#uses=1]
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
tail call void @g(i64 %ins) nounwind
Besides removing phi cycles that reduce to a single value, also remove dead phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
2010-02-13 08:31:44 +08:00
br label %bb2
bb2: ; preds = %bb1, %bb
Last week we were generating code with duplicate induction variables in this test, but the problem seems to have gone away today. Add a check to make sure it doesn't come back. llvm-svn: 96277
2010-02-16 05:56:40 +08:00
; also check for duplicate induction variables (radar 7645034)
; CHECK: subs r{{.*}}, #1
; CHECK-NOT: subs r{{.*}}, #1
; CHECK: pop
Besides removing phi cycles that reduce to a single value, also remove dead phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
2010-02-13 08:31:44 +08:00
%u.0 = phi i64 [ %ins, %bb1 ], [ %u.17, %bb ] ; <i64> [#uses=2]
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %indvar.next, %tmp ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb
return: ; preds = %bb2, %entry
ret i32 undef
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
declare i32 @f()
Add a new pass on machine instructions to optimize away PHI cycles that reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
2010-02-12 09:30:21 +08:00
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
declare void @g(i64)