forked from OSchip/llvm-project
50 lines
1.5 KiB
Plaintext
50 lines
1.5 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
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# Register coalescer is going to eliminate %2:sgpr_32 = COPY %1.sub0 from bb.1
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# by joining %2 and %1.sub0 into %0.sub0 register. Check that when this happen
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# the implicit intialization of %0.sub0 in the bb.2 have undef flag
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# for the MIR to be valid.
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---
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name: coalescing_makes_lane_undefined
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: coalescing_makes_lane_undefined
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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; CHECK: bb.1:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: undef %0.sub0:sgpr_64 = S_MOV_B32 1
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; CHECK: %0.sub1:sgpr_64 = S_MOV_B32 2
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; CHECK: S_BRANCH %bb.3
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: undef %0.sub0:sgpr_64 = IMPLICIT_DEF
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; CHECK: bb.3:
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; CHECK: S_NOP 0, implicit %0.sub0
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; CHECK: S_NOP 0, implicit %0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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successors: %bb.3
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undef %1.sub0:sgpr_64 = S_MOV_B32 1
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%1.sub1:sgpr_64 = S_MOV_B32 2
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%2:sgpr_32 = COPY %1.sub0 ; copy to be joined
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3
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%2:sgpr_32 = IMPLICIT_DEF
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undef %1.sub0:sgpr_64 = IMPLICIT_DEF
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%1.sub1:sgpr_64 = IMPLICIT_DEF
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bb.3:
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S_NOP 0, implicit killed %2
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S_NOP 0, implicit killed %1
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...
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