2017-07-26 19:04:18 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X64
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2009-06-16 14:58:29 +08:00
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declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
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2017-07-26 19:04:18 +08:00
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2011-06-17 11:14:27 +08:00
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define zeroext i1 @a(i32 %x) nounwind {
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2017-07-26 19:04:18 +08:00
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; X86-LABEL: a:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl $3, %ecx
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; X86-NEXT: mull %ecx
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; X86-NEXT: seto %al
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; X86-NEXT: retl
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;
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; X64-LABEL: a:
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; X64: # BB#0:
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; X64-NEXT: movl $3, %ecx
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: mull %ecx
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; X64-NEXT: seto %al
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; X64-NEXT: retq
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2009-06-16 14:58:29 +08:00
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%res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3)
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%obil = extractvalue {i32, i1} %res, 1
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ret i1 %obil
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}
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2011-05-22 02:31:55 +08:00
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define i32 @test2(i32 %a, i32 %b) nounwind readnone {
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2017-07-26 19:04:18 +08:00
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; X86-LABEL: test2:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addl %eax, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # BB#0: # %entry
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: addl %esi, %edi
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; X64-NEXT: leal (%rdi,%rdi), %eax
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; X64-NEXT: retq
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2011-05-22 02:31:55 +08:00
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entry:
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Revert r314886 "[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post required revision changes.)"
It broke the Chromium / SQLite build; see PR34830.
> Summary:
> 1/ Operand folding during complex pattern matching for LEAs has been
> extended, such that it promotes Scale to accommodate similar operand
> appearing in the DAG.
> e.g.
> T1 = A + B
> T2 = T1 + 10
> T3 = T2 + A
> For above DAG rooted at T3, X86AddressMode will no look like
> Base = B , Index = A , Scale = 2 , Disp = 10
>
> 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
> so that if there is an opportunity then complex LEAs (having 3 operands)
> could be factored out.
> e.g.
> leal 1(%rax,%rcx,1), %rdx
> leal 1(%rax,%rcx,2), %rcx
> will be factored as following
> leal 1(%rax,%rcx,1), %rdx
> leal (%rdx,%rcx) , %edx
>
> 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
> thus avoiding creation of any complex LEAs within a loop.
>
> Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy
>
> Reviewed By: lsaba
>
> Subscribers: jmolloy, spatel, igorb, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D35014
llvm-svn: 314919
2017-10-05 01:54:06 +08:00
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%tmp0 = add i32 %b, %a
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%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)
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%tmp2 = extractvalue { i32, i1 } %tmp1, 0
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ret i32 %tmp2
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2011-05-22 02:31:55 +08:00
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}
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define i32 @test3(i32 %a, i32 %b) nounwind readnone {
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2017-07-26 19:04:18 +08:00
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; X86-LABEL: test3:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl $4, %ecx
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; X86-NEXT: mull %ecx
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; X86-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # BB#0: # %entry
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; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: leal (%rdi,%rsi), %eax
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; X64-NEXT: movl $4, %ecx
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; X64-NEXT: mull %ecx
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; X64-NEXT: retq
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2011-05-22 02:31:55 +08:00
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entry:
|
Revert r314886 "[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post required revision changes.)"
It broke the Chromium / SQLite build; see PR34830.
> Summary:
> 1/ Operand folding during complex pattern matching for LEAs has been
> extended, such that it promotes Scale to accommodate similar operand
> appearing in the DAG.
> e.g.
> T1 = A + B
> T2 = T1 + 10
> T3 = T2 + A
> For above DAG rooted at T3, X86AddressMode will no look like
> Base = B , Index = A , Scale = 2 , Disp = 10
>
> 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
> so that if there is an opportunity then complex LEAs (having 3 operands)
> could be factored out.
> e.g.
> leal 1(%rax,%rcx,1), %rdx
> leal 1(%rax,%rcx,2), %rcx
> will be factored as following
> leal 1(%rax,%rcx,1), %rdx
> leal (%rdx,%rcx) , %edx
>
> 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
> thus avoiding creation of any complex LEAs within a loop.
>
> Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy
>
> Reviewed By: lsaba
>
> Subscribers: jmolloy, spatel, igorb, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D35014
llvm-svn: 314919
2017-10-05 01:54:06 +08:00
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|
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%tmp0 = add i32 %b, %a
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%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4)
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%tmp2 = extractvalue { i32, i1 } %tmp1, 0
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ret i32 %tmp2
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2011-05-22 02:31:55 +08:00
|
|
|
}
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