2017-06-11 04:58:43 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2017-06-11 05:13:01 +08:00
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
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2017-06-11 04:58:43 +08:00
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2017-06-11 05:13:01 +08:00
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define <4 x float> @PR32368_128(<4 x float>) {
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; SSE-LABEL: PR32368_128:
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; SSE: # BB#0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: addps %xmm0, %xmm0
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: PR32368_128:
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; AVX1: # BB#0:
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; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR32368_128:
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; AVX2: # BB#0:
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm0
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: PR32368_128:
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; AVX512: # BB#0:
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; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vaddps %xmm0, %xmm0, %xmm0
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; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%2 = bitcast <4 x float> %0 to <4 x i32>
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%3 = and <4 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292>
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%4 = bitcast <4 x i32> %3 to <4 x float>
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%5 = fmul <4 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
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%6 = bitcast <4 x float> %5 to <4 x i32>
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%7 = and <4 x i32> %6, <i32 291, i32 291, i32 291, i32 291>
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%8 = bitcast <4 x i32> %7 to <4 x float>
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ret <4 x float> %8
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}
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define <8 x float> @PR32368_256(<8 x float>) {
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; SSE-LABEL: PR32368_256:
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; SSE: # BB#0:
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; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967004,4294967004,4294967004,4294967004]
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: addps %xmm1, %xmm1
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; SSE-NEXT: addps %xmm0, %xmm0
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; SSE-NEXT: movaps {{.*#+}} xmm2 = [291,291,291,291]
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: PR32368_256:
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; AVX1: # BB#0:
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR32368_256:
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; AVX2: # BB#0:
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: PR32368_256:
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; AVX512: # BB#0:
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; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%2 = bitcast <8 x float> %0 to <8 x i32>
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%3 = and <8 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292>
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%4 = bitcast <8 x i32> %3 to <8 x float>
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%5 = fmul <8 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
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%6 = bitcast <8 x float> %5 to <8 x i32>
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%7 = and <8 x i32> %6, <i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291>
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%8 = bitcast <8 x i32> %7 to <8 x float>
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ret <8 x float> %8
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}
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define <16 x float> @PR32368_512(<16 x float>) {
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; SSE-LABEL: PR32368_512:
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; SSE: # BB#0:
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; SSE-NEXT: movaps {{.*#+}} xmm4 = [4294967004,4294967004,4294967004,4294967004]
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; SSE-NEXT: andps %xmm4, %xmm0
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; SSE-NEXT: andps %xmm4, %xmm1
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; SSE-NEXT: andps %xmm4, %xmm2
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; SSE-NEXT: andps %xmm4, %xmm3
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; SSE-NEXT: addps %xmm3, %xmm3
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; SSE-NEXT: addps %xmm2, %xmm2
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; SSE-NEXT: addps %xmm1, %xmm1
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; SSE-NEXT: addps %xmm0, %xmm0
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; SSE-NEXT: movaps {{.*#+}} xmm4 = [291,291,291,291]
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; SSE-NEXT: andps %xmm4, %xmm0
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; SSE-NEXT: andps %xmm4, %xmm1
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; SSE-NEXT: andps %xmm4, %xmm2
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; SSE-NEXT: andps %xmm4, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: PR32368_512:
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; AVX1: # BB#0:
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; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]
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; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX1-NEXT: vaddps %ymm1, %ymm1, %ymm1
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; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [291,291,291,291,291,291,291,291]
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; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR32368_512:
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; AVX2: # BB#0:
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
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; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX2-NEXT: vaddps %ymm1, %ymm1, %ymm1
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; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
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; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: PR32368_512:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; AVX512-NEXT: vaddps %zmm0, %zmm0, %zmm0
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; AVX512-NEXT: retq
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2017-06-11 04:58:43 +08:00
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%2 = bitcast <16 x float> %0 to <16 x i32>
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%3 = and <16 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292>
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%4 = bitcast <16 x i32> %3 to <16 x float>
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%5 = fmul <16 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
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%6 = bitcast <16 x float> %5 to <16 x i32>
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%7 = and <16 x i32> %6, <i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291>
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%8 = bitcast <16 x i32> %7 to <16 x float>
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ret <16 x float> %8
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}
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