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llvm-project/llvm/test/CodeGen/X86/combine-and.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s
[X86][SSE] Added and+or combine tests currently failing with vectors (and (or x, C), D) -> D if (C & D) == D Part of the yak shaving for D24253 llvm-svn: 280809
2016-09-07 21:40:03 +08:00
[x86] add tests for basic logic op folds llvm-svn: 285520
2016-10-31 02:04:19 +08:00
define i32 @and_self(i32 %x) {
; CHECK-LABEL: and_self:
; CHECK: # BB#0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%and = and i32 %x, %x
ret i32 %and
}
define <4 x i32> @and_self_vec(<4 x i32> %x) {
; CHECK-LABEL: and_self_vec:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%and = and <4 x i32> %x, %x
ret <4 x i32> %and
}
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
;
; Verify that the DAGCombiner is able to fold a vector AND into a blend
; if one of the operands to the AND is a vector of all constants, and each
; constant element is either zero or all-ones.
[X86][SSE] Added and+or combine tests currently failing with vectors (and (or x, C), D) -> D if (C & D) == D Part of the yak shaving for D24253 llvm-svn: 280809
2016-09-07 21:40:03 +08:00
;
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
define <4 x i32> @test1(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test1:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test2(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test2:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test3(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test3:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test4(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test4:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test5(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test5:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test6(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test6:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test7(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test7:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test8(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test8:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test9(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test9:
; CHECK: # BB#0:
; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test10(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test10:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test11(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test11:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test12(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test12:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0>
ret <4 x i32> %1
}
define <4 x i32> @test13(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test13:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test14(<4 x i32> %A) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test14:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
ret <4 x i32> %1
}
define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test15:
; CHECK: # BB#0:
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
%2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0>
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}
define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test16:
; CHECK: # BB#0:
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
%2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1>
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}
define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
[x86] Port this test to use utils/update_llc_test_checks.py. This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. llvm-svn: 228095
2015-02-04 08:58:37 +08:00
; CHECK-LABEL: test17:
; CHECK: # BB#0:
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; CHECK-NEXT: retq
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
2014-11-05 21:04:14 +08:00
%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
%2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0>
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}
[X86][SSE] Added and+or combine tests currently failing with vectors (and (or x, C), D) -> D if (C & D) == D Part of the yak shaving for D24253 llvm-svn: 280809
2016-09-07 21:40:03 +08:00
;
; fold (and (or x, C), D) -> D if (C & D) == D
;
define <2 x i64> @and_or_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: and_or_v2i64:
; CHECK: # BB#0:
[DAGCombiner] Enable AND combines of splatted constant vectors Allow AND combines to use a vector splatted constant as well as a constant scalar. Preliminary part of D24253. llvm-svn: 280926
2016-09-08 20:36:39 +08:00
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [8,8]
[X86][SSE] Added and+or combine tests currently failing with vectors (and (or x, C), D) -> D if (C & D) == D Part of the yak shaving for D24253 llvm-svn: 280809
2016-09-07 21:40:03 +08:00
; CHECK-NEXT: retq
%1 = or <2 x i64> %a0, <i64 255, i64 255>
%2 = and <2 x i64> %1, <i64 8, i64 8>
ret <2 x i64> %2
}
define <4 x i32> @and_or_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: and_or_v4i32:
; CHECK: # BB#0:
[DAGCombiner] Enable AND combines of splatted constant vectors Allow AND combines to use a vector splatted constant as well as a constant scalar. Preliminary part of D24253. llvm-svn: 280926
2016-09-08 20:36:39 +08:00
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3]
[X86][SSE] Added and+or combine tests currently failing with vectors (and (or x, C), D) -> D if (C & D) == D Part of the yak shaving for D24253 llvm-svn: 280809
2016-09-07 21:40:03 +08:00
; CHECK-NEXT: retq
%1 = or <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
%2 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
ret <4 x i32> %2
}
[X86][SSE] Added and+or+zext combine tests for known bits of vectors Part of the yak shaving for D24253 llvm-svn: 280810
2016-09-07 22:00:52 +08:00
;
; known bits folding
;
define <2 x i64> @and_or_zext_v2i32(<2 x i32> %a0) {
; CHECK-LABEL: and_or_zext_v2i32:
; CHECK: # BB#0:
[SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDemandedBits Add the ability to computeKnownBits and SimplifyDemandedBits to extract the known zero/one bits from BUILD_VECTOR, returning the known bits that are shared by every vector element. This is an initial step towards determining the sign bits of a vector (PR29079). Differential Revision: https://reviews.llvm.org/D24253 llvm-svn: 280927
2016-09-08 20:57:51 +08:00
; CHECK-NEXT: xorps %xmm0, %xmm0
[X86][SSE] Added and+or+zext combine tests for known bits of vectors Part of the yak shaving for D24253 llvm-svn: 280810
2016-09-07 22:00:52 +08:00
; CHECK-NEXT: retq
%1 = zext <2 x i32> %a0 to <2 x i64>
%2 = or <2 x i64> %1, <i64 1, i64 1>
%3 = and <2 x i64> %2, <i64 4294967296, i64 4294967296>
ret <2 x i64> %3
}
define <4 x i32> @and_or_zext_v4i16(<4 x i16> %a0) {
; CHECK-LABEL: and_or_zext_v4i16:
; CHECK: # BB#0:
[SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDemandedBits Add the ability to computeKnownBits and SimplifyDemandedBits to extract the known zero/one bits from BUILD_VECTOR, returning the known bits that are shared by every vector element. This is an initial step towards determining the sign bits of a vector (PR29079). Differential Revision: https://reviews.llvm.org/D24253 llvm-svn: 280927
2016-09-08 20:57:51 +08:00
; CHECK-NEXT: xorps %xmm0, %xmm0
[X86][SSE] Added and+or+zext combine tests for known bits of vectors Part of the yak shaving for D24253 llvm-svn: 280810
2016-09-07 22:00:52 +08:00
; CHECK-NEXT: retq
%1 = zext <4 x i16> %a0 to <4 x i32>
%2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
%3 = and <4 x i32> %2, <i32 65536, i32 65536, i32 65536, i32 65536>
ret <4 x i32> %3
}
[X86][SSE] Add ashr + mask test cases. Test cases showing cases where we're missing an opportunity to lshr a value with an extended sign to avoid loading a mask llvm-svn: 298716
2017-03-25 01:25:47 +08:00
;
; known sign bits folding
;
define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) {
; CHECK-LABEL: ashr_mask1_v8i16:
; CHECK: # BB#0:
[X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAI Part 2 of 3. Differential Revision: https://reviews.llvm.org/D31347 llvm-svn: 298780
2017-03-26 03:58:36 +08:00
; CHECK-NEXT: psrlw $15, %xmm0
[X86][SSE] Add ashr + mask test cases. Test cases showing cases where we're missing an opportunity to lshr a value with an extended sign to avoid loading a mask llvm-svn: 298716
2017-03-25 01:25:47 +08:00
; CHECK-NEXT: retq
%1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %2
}
define <4 x i32> @ashr_mask7_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: ashr_mask7_v4i32:
; CHECK: # BB#0:
; CHECK-NEXT: psrad $31, %xmm0
[X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAI Part 2 of 3. Differential Revision: https://reviews.llvm.org/D31347 llvm-svn: 298780
2017-03-26 03:58:36 +08:00
; CHECK-NEXT: psrld $29, %xmm0
[X86][SSE] Add ashr + mask test cases. Test cases showing cases where we're missing an opportunity to lshr a value with an extended sign to avoid loading a mask llvm-svn: 298716
2017-03-25 01:25:47 +08:00
; CHECK-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 31, i32 31, i32 31, i32 31>
%2 = and <4 x i32> %1, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %2
}
[X86][SSE] Add 'redundant pand' test case from PR34620 llvm-svn: 313632
2017-09-19 22:02:16 +08:00
;
; SimplifyDemandedBits
;
; PR34620 - redundant PAND after vector shift of a byte vector (PSRLW)
define <16 x i8> @PR34620(<16 x i8> %a0, <16 x i8> %a1) {
; CHECK-LABEL: PR34620:
; CHECK: # BB#0:
; CHECK-NEXT: psrlw $1, %xmm0
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = lshr <16 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%3 = add <16 x i8> %2, %a1
ret <16 x i8> %3
}