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llvm-project/llvm/test/CodeGen/X86/add-of-carry.ll

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[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
[x86] don't blindly transform SETB into SBB I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
2017-03-13 02:28:48 +08:00
; These tests use adc/sbb in place of set+add/sub. Should this transform
; be enabled by micro-architecture rather than as part of generic lowering/isel?
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization (sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. llvm-svn: 114460
2010-09-22 02:41:19 +08:00
; <rdar://problem/8449754>
improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
2010-12-20 06:08:31 +08:00
define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test1:
[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00
; CHECK: # BB#0:
[DAGCombine] (add/uaddo X, Carry) -> (addcarry X, 0, Carry) Summary: This enables further transforms. Depends on D32916 Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32925 llvm-svn: 304401
2017-06-01 18:42:39 +08:00
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
[DAGCombine] (add/uaddo X, Carry) -> (addcarry X, 0, Carry) Summary: This enables further transforms. Depends on D32916 Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32925 llvm-svn: 304401
2017-06-01 18:42:39 +08:00
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: adcl %ecx, %eax
[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00
; CHECK-NEXT: retl
[InstCombine][CodeGenPrep] Create llvm.uadd.with.overflow in CGP. Summary: This change moves creating calls to `llvm.uadd.with.overflow` from InstCombine to CodeGenPrep. Combining overflow check patterns into calls to the said intrinsic in InstCombine inhibits optimization because it introduces an intrinsic call that not all other transforms and analyses understand. Depends on D8888. Reviewers: majnemer, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8889 llvm-svn: 234638
2015-04-11 05:07:09 +08:00
%add4 = add i32 %x, %sum
%cmp = icmp ult i32 %add4, %x
improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
2010-12-20 06:08:31 +08:00
%inc = zext i1 %cmp to i32
[InstCombine][CodeGenPrep] Create llvm.uadd.with.overflow in CGP. Summary: This change moves creating calls to `llvm.uadd.with.overflow` from InstCombine to CodeGenPrep. Combining overflow check patterns into calls to the said intrinsic in InstCombine inhibits optimization because it introduces an intrinsic call that not all other transforms and analyses understand. Depends on D8888. Reviewers: majnemer, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8889 llvm-svn: 234638
2015-04-11 05:07:09 +08:00
%z.0 = add i32 %add4, %inc
improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
2010-12-20 06:08:31 +08:00
ret i32 %z.0
}
(For X86) Enhancement to add-carray/sub-borrow (adc/sbb) optimization. The adc/sbb optimization is to able to convert following expression into a single adc/sbb instruction: (ult) ... = x + 1 // where the ult is unsigned-less-than comparison (ult) ... = x - 1 This change is to flip the "x >u y" (i.e. ugt comparison) in order to expose the adc/sbb opportunity. llvm-svn: 167180
2012-11-01 07:11:48 +08:00
; <rdar://problem/12579915>
[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00
[InstCombine][CodeGenPrep] Create llvm.uadd.with.overflow in CGP. Summary: This change moves creating calls to `llvm.uadd.with.overflow` from InstCombine to CodeGenPrep. Combining overflow check patterns into calls to the said intrinsic in InstCombine inhibits optimization because it introduces an intrinsic call that not all other transforms and analyses understand. Depends on D8888. Reviewers: majnemer, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8889 llvm-svn: 234638
2015-04-11 05:07:09 +08:00
define i32 @test2(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {
[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00
; CHECK-LABEL: test2:
; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: sbbl $0, %eax
; CHECK-NEXT: retl
(For X86) Enhancement to add-carray/sub-borrow (adc/sbb) optimization. The adc/sbb optimization is to able to convert following expression into a single adc/sbb instruction: (ult) ... = x + 1 // where the ult is unsigned-less-than comparison (ult) ... = x - 1 This change is to flip the "x >u y" (i.e. ugt comparison) in order to expose the adc/sbb opportunity. llvm-svn: 167180
2012-11-01 07:11:48 +08:00
%cmp = icmp ugt i32 %x, %y
%dec = sext i1 %cmp to i32
%dec.res = add nsw i32 %dec, %res
ret i32 %dec.res
}
[x86] regenerate checks; NFC llvm-svn: 296877
2017-03-04 00:34:35 +08:00