forked from OSchip/llvm-project
72 lines
2.6 KiB
LLVM
72 lines
2.6 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: {
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; CHECK: loop0(.LBB
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; CHECK-NOT: loop0(##.LBB
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
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target triple = "hexagon"
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define i32 @q6zip_uncompress(i8* %out_buf, i32* %out_buf_size, i8* %in_buf, i32 %in_buf_size, i8* nocapture %dict, i32 %dict_size) nounwind {
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entry:
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%0 = bitcast i8* %in_buf to i32*
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%incdec.ptr = getelementptr inbounds i8, i8* %in_buf, i32 4
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%1 = load i32, i32* %0, align 4, !tbaa !0
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%2 = ptrtoint i8* %incdec.ptr to i32
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%and.i = and i32 %2, 31
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%sub.i = sub i32 %2, %and.i
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%3 = inttoptr i32 %sub.i to i8*
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%add.i = add i32 %in_buf_size, 31
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%sub2.i = add i32 %add.i, %and.i
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%div.i = lshr i32 %sub2.i, 5
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%4 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 32, i32 %div.i) nounwind
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%5 = tail call i64 @llvm.hexagon.A4.combineir(i32 32, i32 %4) nounwind
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tail call void asm sideeffect "l2fetch($0,$1)", "r,r,~{memory}"(i8* %3, i64 %5) nounwind, !srcloc !3
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%6 = ptrtoint i8* %out_buf to i32
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br label %for.body.i
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for.body.i: ; preds = %for.body.i, %entry
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%i.02.i = phi i32 [ 0, %entry ], [ %inc.i, %for.body.i ]
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%addr.addr.01.i = phi i32 [ %6, %entry ], [ %add.i14, %for.body.i ]
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tail call void asm sideeffect "dczeroa($0)", "r"(i32 %addr.addr.01.i) nounwind, !srcloc !4
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%add.i14 = add i32 %addr.addr.01.i, 32
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%inc.i = add i32 %i.02.i, 1
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%exitcond.i = icmp eq i32 %inc.i, 128
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br i1 %exitcond.i, label %while.cond.preheader, label %for.body.i
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while.cond.preheader: ; preds = %for.body.i
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%and = and i32 %1, 3
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switch i32 %and, label %infloop.preheader [
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i32 0, label %exit_inflate.split
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i32 2, label %if.then.preheader
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]
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if.then.preheader: ; preds = %while.cond.preheader
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br label %if.then
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infloop.preheader: ; preds = %while.cond.preheader
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br label %infloop
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if.then: ; preds = %if.then.preheader, %if.then
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tail call void @llvm.prefetch(i8* %incdec.ptr, i32 0, i32 3, i32 1)
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br label %if.then
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exit_inflate.split: ; preds = %while.cond.preheader
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ret i32 0
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infloop: ; preds = %infloop.preheader, %infloop
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br label %infloop
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}
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declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind
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declare i64 @llvm.hexagon.A4.combineir(i32, i32) nounwind readnone
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declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) nounwind readnone
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!0 = !{!"long", !1}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{i32 18362}
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!4 = !{i32 18893}
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