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llvm-project/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll

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[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
2017-05-12 00:54:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
Recommit r310809 with a fix for the spill problem This patch re-commits the patch that was pulled out due to a problem it caused, but with a fix for the problem. The fix was reviewed separately by Eric Christopher and Hal Finkel. Differential Revision: https://reviews.llvm.org/D38054 llvm-svn: 313978
2017-09-22 19:50:25 +08:00
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
2017-05-12 00:54:23 +08:00
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_z(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Recommit r310809 with a fix for the spill problem This patch re-commits the patch that was pulled out due to a problem it caused, but with a fix for the problem. The fix was reviewed separately by Eric Christopher and Hal Finkel. Differential Revision: https://reviews.llvm.org/D38054 llvm-svn: 313978
2017-09-22 19:50:25 +08:00
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
2017-05-12 00:54:23 +08:00
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
Recommit r310809 with a fix for the spill problem This patch re-commits the patch that was pulled out due to a problem it caused, but with a fix for the problem. The fix was reviewed separately by Eric Christopher and Hal Finkel. Differential Revision: https://reviews.llvm.org/D38054 llvm-svn: 313978
2017-09-22 19:50:25 +08:00
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
2017-05-12 00:54:23 +08:00
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
Recommit r310809 with a fix for the spill problem This patch re-commits the patch that was pulled out due to a problem it caused, but with a fix for the problem. The fix was reviewed separately by Eric Christopher and Hal Finkel. Differential Revision: https://reviews.llvm.org/D38054 llvm-svn: 313978
2017-09-22 19:50:25 +08:00
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
2017-05-12 00:54:23 +08:00
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}