llvm-project/llvm/test/CodeGen/PowerPC/vec_fneg.ll

; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp

define void @t(<4 x float>* %A) {
	%tmp2 = load <4 x float>* %A
	%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
	store <4 x float> %tmp3, <4 x float>* %A
	ret void
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293 2009-09-09 08:09:15 +08:00			`; RUN: llc < %s -march=ppc32 -mcpu=g5 \| grep vsubfp`
New test case. llvm-svn: 40587 2007-07-30 15:52:03 +08:00
			`define void @t(<4 x float>* %A) {`
			`%tmp2 = load <4 x float>* %A`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 06:49:04 +08:00			`%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2`
New test case. llvm-svn: 40587 2007-07-30 15:52:03 +08:00			`store <4 x float> %tmp3, <4 x float>* %A`
			`ret void`
			`}`