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llvm-project/llvm/test/CodeGen/Mips/zeroreg.ll

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[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6
; RUN: llc < %s -march=mipsel -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
; RUN: llc < %s -march=mipsel -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
; RUN: llc < %s -march=mipsel -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
@g1 = external global i32
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define i32 @sel_icmp_nez_i32_z0(i32 %s) nounwind readonly {
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
entry:
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
; ALL-LABEL: sel_icmp_nez_i32_z0:
; 32-CMOV: lw $2, 0(${{[0-9]+}})
; 32-CMOV: movn $2, $zero, $4
; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 32R6: seleqz $2, $[[R0]], $4
; 64-CMOV: lw $2, 0(${{[0-9]+}})
; 64-CMOV: movn $2, $zero, $4
; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 64R6: seleqz $2, $[[R0]], $4
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
%tobool = icmp ne i32 %s, 0
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 180796
2013-05-01 01:52:57 +08:00
%0 = load i32* @g1, align 4
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
%cond = select i1 %tobool, i32 0, i32 %0
ret i32 %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define i32 @sel_icmp_nez_i32_z1(i32 %s) nounwind readonly {
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
entry:
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
; ALL-LABEL: sel_icmp_nez_i32_z1:
; 32-CMOV: lw $2, 0(${{[0-9]+}})
; 32-CMOV: movz $2, $zero, $4
; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 32R6: selnez $2, $[[R0]], $4
; 64-CMOV: lw $2, 0(${{[0-9]+}})
; 64-CMOV: movz $2, $zero, $4
; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 64R6: selnez $2, $[[R0]], $4
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
%tobool = icmp ne i32 %s, 0
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 180796
2013-05-01 01:52:57 +08:00
%0 = load i32* @g1, align 4
Test case for r152280, r152285 and r152290. llvm-svn: 152292
2012-03-08 11:32:42 +08:00
%cond = select i1 %tobool, i32 %0, i32 0
ret i32 %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
@g2 = external global i64
define i64 @sel_icmp_nez_i64_z0(i64 %s) nounwind readonly {
entry:
; ALL-LABEL: sel_icmp_nez_i64_z0:
; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})
; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}})
; 32-CMOV-DAG: movn $[[R0]], $zero, $4
; 32-CMOV-DAG: movn $[[R1]], $zero, $4
; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; 32R6-DAG: or $[[CC:[0-9]+]], $4, $5
; 32R6-DAG: seleqz $2, $[[R0]], $[[CC]]
; 32R6-DAG: seleqz $3, $[[R1]], $[[CC]]
; 64-CMOV: ld $2, 0(${{[0-9]+}})
; 64-CMOV: movn $2, $zero, $4
; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 64R6: seleqz $2, $[[R0]], $4
%tobool = icmp ne i64 %s, 0
%0 = load i64* @g2, align 4
%cond = select i1 %tobool, i64 0, i64 %0
ret i64 %cond
}
define i64 @sel_icmp_nez_i64_z1(i64 %s) nounwind readonly {
entry:
; ALL-LABEL: sel_icmp_nez_i64_z1:
; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})
; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}})
; 32-CMOV-DAG: movz $[[R0]], $zero, $4
; 32-CMOV-DAG: movz $[[R1]], $zero, $4
; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; 32R6-DAG: or $[[CC:[0-9]+]], $4, $5
; 32R6-DAG: selnez $2, $[[R0]], $[[CC]]
; 32R6-DAG: selnez $3, $[[R1]], $[[CC]]
; 64-CMOV: ld $2, 0(${{[0-9]+}})
; 64-CMOV: movz $2, $zero, $4
; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}})
; 64R6: selnez $2, $[[R0]], $4
%tobool = icmp ne i64 %s, 0
%0 = load i64* @g2, align 4
%cond = select i1 %tobool, i64 %0, i64 0
ret i64 %cond
}