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llvm-project/llvm/test/CodeGen/Mips/mips64fpimm0.ll

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[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point Summary: Two exceptions to this: test/CodeGen/Mips/octeon.ll test/CodeGen/Mips/octeon_popcnt.ll these test extensions to MIPS64 One test is altered for MIPS-IV: test/CodeGen/Mips/mips64countleading.ll Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests that dclo/dclz are not emitted. Four tests fail and are not in this patch: test/CodeGen/Mips/abicalls.ll test/CodeGen/Mips/fcopysign-f32-f64.ll test/CodeGen/Mips/fcopysign.ll test/CodeGen/Mips/stack-alignment.ll Depends on D3343 Reviewers: matheusalmeida, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3344 llvm-svn: 206185
2014-04-15 00:00:28 +08:00
; RUN: llc < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s
Add code in MipsDAGToDAGISel for selecting constant +0.0. MIPS64 can generate constant +0.0 with a single DMTC1 instruction. llvm-svn: 146999
2011-12-21 06:25:50 +08:00
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
define double @foo1() nounwind readnone {
entry:
; CHECK: dmtc1 $zero
ret double 0.000000e+00
}