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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sd...

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GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[globalisel][tablegen] Correct matching of intrinsic ID's. TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
2017-07-11 16:57:29 +08:00
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @sdiv_s32_gpr() { ret void }
...
---
# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
name: sdiv_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: %w0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; CHECK-LABEL: name: sdiv_s32_gpr
; CHECK: registers:
; CHECK-NEXT: id: 0, class: gpr32
; CHECK-NEXT: id: 1, class: gpr32
; CHECK-NEXT: id: 2, class: gpr32
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
; CHECK: [[SDIVWr:%[0-9]+]] = SDIVWr [[COPY]], [[COPY1]]
; CHECK: %w0 = COPY [[SDIVWr]]
[globalisel][tablegen] Correct matching of intrinsic ID's. TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
2017-07-11 16:57:29 +08:00
%0(s32) = COPY %w0
%1(s32) = COPY %w1
%2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
%w0 = COPY %2(s32)
...