2017-10-19 07:33:31 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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2017-03-16 00:29:37 +08:00
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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2017-09-13 05:04:10 +08:00
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define void @fptrunc_s16_s32_fpr() { ret void }
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define void @fptrunc_s16_s64_fpr() { ret void }
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define void @fptrunc_s32_s64_fpr() { ret void }
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2017-09-13 05:04:11 +08:00
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define void @fpext_s32_s16_fpr() { ret void }
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define void @fpext_s64_s16_fpr() { ret void }
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define void @fpext_s64_s32_fpr() { ret void }
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2017-03-16 00:29:37 +08:00
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define void @sitofp_s32_s32_fpr() { ret void }
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define void @sitofp_s32_s64_fpr() { ret void }
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define void @sitofp_s64_s32_fpr() { ret void }
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define void @sitofp_s64_s64_fpr() { ret void }
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define void @uitofp_s32_s32_fpr() { ret void }
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define void @uitofp_s32_s64_fpr() { ret void }
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define void @uitofp_s64_s32_fpr() { ret void }
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define void @uitofp_s64_s64_fpr() { ret void }
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define void @fptosi_s32_s32_gpr() { ret void }
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define void @fptosi_s32_s64_gpr() { ret void }
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define void @fptosi_s64_s32_gpr() { ret void }
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define void @fptosi_s64_s64_gpr() { ret void }
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define void @fptoui_s32_s32_gpr() { ret void }
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define void @fptoui_s32_s64_gpr() { ret void }
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define void @fptoui_s64_s32_gpr() { ret void }
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define void @fptoui_s64_s64_gpr() { ret void }
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...
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---
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2017-09-13 05:04:10 +08:00
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name: fptrunc_s16_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %s0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: fptrunc_s16_s32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr32
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; CHECK-NEXT: id: 1, class: fpr16
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; CHECK: [[COPY:%[0-9]+]] = COPY %s0
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; CHECK: [[FCVTHSr:%[0-9]+]] = FCVTHSr [[COPY]]
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; CHECK: %h0 = COPY [[FCVTHSr]]
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2017-09-13 05:04:10 +08:00
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%0(s32) = COPY %s0
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%1(s16) = G_FPTRUNC %0
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%h0 = COPY %1(s16)
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...
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---
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name: fptrunc_s16_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %d0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: fptrunc_s16_s64_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr64
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; CHECK-NEXT: id: 1, class: fpr16
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; CHECK: [[COPY:%[0-9]+]] = COPY %d0
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; CHECK: [[FCVTHDr:%[0-9]+]] = FCVTHDr [[COPY]]
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; CHECK: %h0 = COPY [[FCVTHDr]]
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2017-09-13 05:04:10 +08:00
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%0(s64) = COPY %d0
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%1(s16) = G_FPTRUNC %0
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%h0 = COPY %1(s16)
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...
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---
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name: fptrunc_s32_s64_fpr
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2017-03-16 00:29:37 +08:00
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %d0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: fptrunc_s32_s64_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr64
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %d0
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; CHECK: [[FCVTSDr:%[0-9]+]] = FCVTSDr [[COPY]]
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; CHECK: %s0 = COPY [[FCVTSDr]]
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2017-03-16 00:29:37 +08:00
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%0(s64) = COPY %d0
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%1(s32) = G_FPTRUNC %0
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2017-03-20 00:13:00 +08:00
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%s0 = COPY %1(s32)
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2017-03-16 00:29:37 +08:00
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...
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---
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2017-09-13 05:04:11 +08:00
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name: fpext_s32_s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %h0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: fpext_s32_s16_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr16
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %h0
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; CHECK: [[FCVTSHr:%[0-9]+]] = FCVTSHr [[COPY]]
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; CHECK: %s0 = COPY [[FCVTSHr]]
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2017-09-13 05:04:11 +08:00
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%0(s16) = COPY %h0
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%1(s32) = G_FPEXT %0
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%s0 = COPY %1(s32)
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...
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---
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name: fpext_s64_s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %h0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: fpext_s64_s16_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr16
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %h0
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; CHECK: [[FCVTDHr:%[0-9]+]] = FCVTDHr [[COPY]]
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; CHECK: %d0 = COPY [[FCVTDHr]]
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2017-09-13 05:04:11 +08:00
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%0(s16) = COPY %h0
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%1(s64) = G_FPEXT %0
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%d0 = COPY %1(s64)
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...
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---
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name: fpext_s64_s32_fpr
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2017-03-16 00:29:37 +08:00
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %d0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: fpext_s64_s32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr32
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %s0
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; CHECK: [[FCVTDSr:%[0-9]+]] = FCVTDSr [[COPY]]
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; CHECK: %d0 = COPY [[FCVTDSr]]
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2017-03-16 00:29:37 +08:00
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%0(s32) = COPY %s0
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%1(s64) = G_FPEXT %0
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2017-03-20 00:13:00 +08:00
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%d0 = COPY %1(s64)
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2017-03-16 00:29:37 +08:00
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...
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---
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name: sitofp_s32_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %w0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: sitofp_s32_s32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr32
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %w0
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; CHECK: [[SCVTFUWSri:%[0-9]+]] = SCVTFUWSri [[COPY]]
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; CHECK: %s0 = COPY [[SCVTFUWSri]]
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2017-03-16 00:29:37 +08:00
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%0(s32) = COPY %w0
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%1(s32) = G_SITOFP %0
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2017-03-20 00:13:00 +08:00
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%s0 = COPY %1(s32)
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2017-03-16 00:29:37 +08:00
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...
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---
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name: sitofp_s32_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %x0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: sitofp_s32_s64_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr64
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %x0
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; CHECK: [[SCVTFUXSri:%[0-9]+]] = SCVTFUXSri [[COPY]]
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; CHECK: %s0 = COPY [[SCVTFUXSri]]
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2017-03-16 00:29:37 +08:00
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%0(s64) = COPY %x0
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%1(s32) = G_SITOFP %0
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2017-03-20 00:13:00 +08:00
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%s0 = COPY %1(s32)
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2017-03-16 00:29:37 +08:00
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...
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---
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name: sitofp_s64_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %w0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: sitofp_s64_s32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr32
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %w0
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; CHECK: [[SCVTFUWDri:%[0-9]+]] = SCVTFUWDri [[COPY]]
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; CHECK: %d0 = COPY [[SCVTFUWDri]]
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2017-03-16 00:29:37 +08:00
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%0(s32) = COPY %w0
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%1(s64) = G_SITOFP %0
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2017-03-20 00:13:00 +08:00
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%d0 = COPY %1(s64)
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2017-03-16 00:29:37 +08:00
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...
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---
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name: sitofp_s64_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %x0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: sitofp_s64_s64_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr64
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %x0
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; CHECK: [[SCVTFUXDri:%[0-9]+]] = SCVTFUXDri [[COPY]]
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; CHECK: %d0 = COPY [[SCVTFUXDri]]
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2017-03-16 00:29:37 +08:00
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%0(s64) = COPY %x0
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%1(s64) = G_SITOFP %0
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2017-03-20 00:13:00 +08:00
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%d0 = COPY %1(s64)
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2017-03-16 00:29:37 +08:00
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...
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---
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name: uitofp_s32_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %w0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: uitofp_s32_s32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr32
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %w0
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; CHECK: [[UCVTFUWSri:%[0-9]+]] = UCVTFUWSri [[COPY]]
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; CHECK: %s0 = COPY [[UCVTFUWSri]]
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2017-03-16 00:29:37 +08:00
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%0(s32) = COPY %w0
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%1(s32) = G_UITOFP %0
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2017-03-20 00:13:00 +08:00
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%s0 = COPY %1(s32)
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2017-03-16 00:29:37 +08:00
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...
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---
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name: uitofp_s32_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: %x0
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2017-10-19 07:33:31 +08:00
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; CHECK-LABEL: name: uitofp_s32_s64_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr64
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|
|
; CHECK-NEXT: id: 1, class: fpr32
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
|
|
|
; CHECK: [[UCVTFUXSri:%[0-9]+]] = UCVTFUXSri [[COPY]]
|
|
|
|
; CHECK: %s0 = COPY [[UCVTFUXSri]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s64) = COPY %x0
|
|
|
|
%1(s32) = G_UITOFP %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%s0 = COPY %1(s32)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: uitofp_s64_s32_fpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: fpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %w0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: uitofp_s64_s32_fpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: gpr32
|
|
|
|
; CHECK-NEXT: id: 1, class: fpr64
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
|
|
|
; CHECK: [[UCVTFUWDri:%[0-9]+]] = UCVTFUWDri [[COPY]]
|
|
|
|
; CHECK: %d0 = COPY [[UCVTFUWDri]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s32) = COPY %w0
|
|
|
|
%1(s64) = G_UITOFP %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%d0 = COPY %1(s64)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: uitofp_s64_s64_fpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: fpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %x0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: uitofp_s64_s64_fpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: gpr64
|
|
|
|
; CHECK-NEXT: id: 1, class: fpr64
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
|
|
|
; CHECK: [[UCVTFUXDri:%[0-9]+]] = UCVTFUXDri [[COPY]]
|
|
|
|
; CHECK: %d0 = COPY [[UCVTFUXDri]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s64) = COPY %x0
|
|
|
|
%1(s64) = G_UITOFP %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%d0 = COPY %1(s64)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptosi_s32_s32_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %s0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptosi_s32_s32_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr32
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr32
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
|
|
|
; CHECK: [[FCVTZSUWSr:%[0-9]+]] = FCVTZSUWSr [[COPY]]
|
|
|
|
; CHECK: %w0 = COPY [[FCVTZSUWSr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s32) = COPY %s0
|
|
|
|
%1(s32) = G_FPTOSI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%w0 = COPY %1(s32)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptosi_s32_s64_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %d0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptosi_s32_s64_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr64
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr32
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
|
|
|
; CHECK: [[FCVTZSUWDr:%[0-9]+]] = FCVTZSUWDr [[COPY]]
|
|
|
|
; CHECK: %w0 = COPY [[FCVTZSUWDr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s64) = COPY %d0
|
|
|
|
%1(s32) = G_FPTOSI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%w0 = COPY %1(s32)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptosi_s64_s32_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %s0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptosi_s64_s32_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr32
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr64
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
|
|
|
; CHECK: [[FCVTZSUXSr:%[0-9]+]] = FCVTZSUXSr [[COPY]]
|
|
|
|
; CHECK: %x0 = COPY [[FCVTZSUXSr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s32) = COPY %s0
|
|
|
|
%1(s64) = G_FPTOSI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%x0 = COPY %1(s64)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptosi_s64_s64_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %d0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptosi_s64_s64_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr64
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr64
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
|
|
|
; CHECK: [[FCVTZSUXDr:%[0-9]+]] = FCVTZSUXDr [[COPY]]
|
|
|
|
; CHECK: %x0 = COPY [[FCVTZSUXDr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s64) = COPY %d0
|
|
|
|
%1(s64) = G_FPTOSI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%x0 = COPY %1(s64)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptoui_s32_s32_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %s0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptoui_s32_s32_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr32
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr32
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
|
|
|
; CHECK: [[FCVTZUUWSr:%[0-9]+]] = FCVTZUUWSr [[COPY]]
|
|
|
|
; CHECK: %w0 = COPY [[FCVTZUUWSr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s32) = COPY %s0
|
|
|
|
%1(s32) = G_FPTOUI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%w0 = COPY %1(s32)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptoui_s32_s64_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %d0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptoui_s32_s64_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr64
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr32
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
|
|
|
; CHECK: [[FCVTZUUWDr:%[0-9]+]] = FCVTZUUWDr [[COPY]]
|
|
|
|
; CHECK: %w0 = COPY [[FCVTZUUWDr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s64) = COPY %d0
|
|
|
|
%1(s32) = G_FPTOUI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%w0 = COPY %1(s32)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptoui_s64_s32_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %s0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptoui_s64_s32_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr32
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr64
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
|
|
|
; CHECK: [[FCVTZUUXSr:%[0-9]+]] = FCVTZUUXSr [[COPY]]
|
|
|
|
; CHECK: %x0 = COPY [[FCVTZUUXSr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s32) = COPY %s0
|
|
|
|
%1(s64) = G_FPTOUI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%x0 = COPY %1(s64)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fptoui_s64_s64_gpr
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
liveins: %d0
|
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; CHECK-LABEL: name: fptoui_s64_s64_gpr
|
|
|
|
; CHECK: registers:
|
|
|
|
; CHECK-NEXT: id: 0, class: fpr64
|
|
|
|
; CHECK-NEXT: id: 1, class: gpr64
|
|
|
|
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
|
|
|
; CHECK: [[FCVTZUUXDr:%[0-9]+]] = FCVTZUUXDr [[COPY]]
|
|
|
|
; CHECK: %x0 = COPY [[FCVTZUUXDr]]
|
2017-03-16 00:29:37 +08:00
|
|
|
%0(s64) = COPY %d0
|
|
|
|
%1(s64) = G_FPTOUI %0
|
2017-03-20 00:13:00 +08:00
|
|
|
%x0 = COPY %1(s64)
|
2017-03-16 00:29:37 +08:00
|
|
|
...
|