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llvm-project/llvm/test/CodeGen/X86/movddup-load-fold.ll

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[x86] move test for movddup; NFC This adds an AVX512 run as suggested in D55936. The test didn't really belong with other build vector tests because that's not the pattern here. I don't see much value in adding 64-bit RUNs because they wouldn't exercise the isel patterns that we're aiming to expose. llvm-svn: 349920
2018-12-22 00:08:27 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=i686-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: llc < %s -mtriple=i686-- -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512VL
; Test an isel pattern for a splatted VZLOAD.
define <4 x float> @movddup_load_fold(float %x, float %y) {
; SSE-LABEL: movddup_load_fold:
; SSE: # %bb.0:
[x86] add load fold patterns for movddup with vzext_load The missed load folding noticed in D55898 is visible independent of that change either with an adjusted IR pattern to start or with AVX2/AVX512 (where the build vector becomes a broadcast first; movddup is not produced until we get into isel via tablegen patterns). Differential Revision: https://reviews.llvm.org/D55936 llvm-svn: 350005
2018-12-23 00:59:02 +08:00
; SSE-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
[x86] move test for movddup; NFC This adds an AVX512 run as suggested in D55936. The test didn't really belong with other build vector tests because that's not the pattern here. I don't see much value in adding 64-bit RUNs because they wouldn't exercise the isel patterns that we're aiming to expose. llvm-svn: 349920
2018-12-22 00:08:27 +08:00
; SSE-NEXT: retl
;
; AVX-LABEL: movddup_load_fold:
; AVX: # %bb.0:
[x86] add load fold patterns for movddup with vzext_load The missed load folding noticed in D55898 is visible independent of that change either with an adjusted IR pattern to start or with AVX2/AVX512 (where the build vector becomes a broadcast first; movddup is not produced until we get into isel via tablegen patterns). Differential Revision: https://reviews.llvm.org/D55936 llvm-svn: 350005
2018-12-23 00:59:02 +08:00
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
[x86] move test for movddup; NFC This adds an AVX512 run as suggested in D55936. The test didn't really belong with other build vector tests because that's not the pattern here. I don't see much value in adding 64-bit RUNs because they wouldn't exercise the isel patterns that we're aiming to expose. llvm-svn: 349920
2018-12-22 00:08:27 +08:00
; AVX-NEXT: retl
%i0 = insertelement <4 x float> zeroinitializer, float %x, i32 0
%i1 = insertelement <4 x float> %i0, float %y, i32 1
%dup = shufflevector <4 x float> %i1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x float> %dup
}