2012-02-17 16:55:11 +08:00
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//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
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2007-06-06 15:42:06 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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//
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// This file defines an instruction selector for the MIPS target.
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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2012-12-04 00:50:05 +08:00
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#include "MCTargetDesc/MipsBaseInfo.h"
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2012-01-25 11:01:35 +08:00
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#include "MipsAnalyzeImmediate.h"
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2007-11-05 11:02:32 +08:00
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#include "MipsMachineFunction.h"
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2007-06-06 15:42:06 +08:00
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 12:13:23 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2012-02-28 10:55:02 +08:00
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/CFG.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/Support/Debug.h"
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2009-07-09 04:53:28 +08:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetMachine.h"
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2007-06-06 15:42:06 +08:00
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using namespace llvm;
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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// Instruction Selector Implementation
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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namespace {
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2009-10-25 14:33:48 +08:00
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class MipsDAGToDAGISel : public SelectionDAGISel {
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2007-06-06 15:42:06 +08:00
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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const MipsSubtarget &Subtarget;
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2011-03-05 01:51:39 +08:00
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2007-06-06 15:42:06 +08:00
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public:
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2008-07-08 02:00:37 +08:00
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explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
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2009-01-16 03:20:50 +08:00
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SelectionDAGISel(tm),
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2008-10-04 00:55:19 +08:00
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TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
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2011-03-05 01:51:39 +08:00
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2007-06-06 15:42:06 +08:00
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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2011-03-05 01:51:39 +08:00
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}
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2007-06-06 15:42:06 +08:00
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2012-02-25 06:34:47 +08:00
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virtual bool runOnMachineFunction(MachineFunction &MF);
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2011-03-05 01:51:39 +08:00
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private:
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2007-06-06 15:42:06 +08:00
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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2009-06-04 04:30:14 +08:00
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const MipsTargetMachine &getTargetMachine() {
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return static_cast<const MipsTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const MipsInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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2011-12-21 07:10:57 +08:00
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2012-10-28 14:02:37 +08:00
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SDValue getMips16SPAliasReg();
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void getMips16SPRefReg(SDNode *parent, SDValue &AliasReg);
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2011-12-21 07:10:57 +08:00
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std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
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EVT Ty, bool HasLo, bool HasHi);
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2010-01-05 09:24:18 +08:00
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SDNode *Select(SDNode *N);
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2007-06-06 15:42:06 +08:00
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// Complex Pattern.
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2013-02-16 05:20:45 +08:00
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/// (reg + imm).
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2013-02-16 08:14:37 +08:00
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bool selectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) const;
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2013-02-16 05:20:45 +08:00
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/// Fall back on this function if all else fails.
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2013-02-16 08:14:37 +08:00
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bool selectAddrDefault(SDValue Addr, SDValue &Base, SDValue &Offset) const;
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2013-02-16 05:20:45 +08:00
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/// Match integer address pattern.
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2013-02-16 08:14:37 +08:00
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bool selectIntAddr(SDValue Addr, SDValue &Base, SDValue &Offset) const;
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2007-06-06 15:42:06 +08:00
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2012-10-28 14:02:37 +08:00
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bool SelectAddr16(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset,
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SDValue &Alias);
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2011-12-08 04:15:01 +08:00
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// getImm - Return a target constant with the specified value.
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2011-12-08 04:10:24 +08:00
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inline SDValue getImm(const SDNode *Node, unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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2007-06-06 15:42:06 +08:00
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}
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2011-06-21 08:40:49 +08:00
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2012-03-08 09:51:59 +08:00
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void ProcessFunctionAfterISel(MachineFunction &MF);
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bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
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2012-02-25 06:34:47 +08:00
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void InitGlobalBaseReg(MachineFunction &MF);
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2012-10-28 14:02:37 +08:00
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void InitMips16SPAliasReg(MachineFunction &MF);
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2012-02-25 06:34:47 +08:00
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2011-06-21 08:40:49 +08:00
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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2007-06-06 15:42:06 +08:00
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};
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}
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2012-02-25 06:34:47 +08:00
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// Insert instructions to initialize the global base register in the
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// first MBB of the function. When the ABI is O32 and the relocation model is
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// PIC, the necessary instructions are emitted later to prevent optimization
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// passes from moving them.
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void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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2012-02-28 15:46:26 +08:00
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2012-07-25 11:16:47 +08:00
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if (!MipsFI->globalBaseRegSet())
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2012-06-27 08:20:39 +08:00
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return;
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2012-02-25 06:34:47 +08:00
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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2012-07-24 07:45:54 +08:00
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unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
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2012-07-25 11:16:47 +08:00
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const TargetRegisterClass *RC;
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2012-06-22 04:39:10 +08:00
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2012-07-25 11:16:47 +08:00
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if (Subtarget.isABI_N64())
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RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
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else if (Subtarget.inMips16Mode())
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RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
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else
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RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
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2012-07-24 07:45:54 +08:00
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2012-05-12 08:17:17 +08:00
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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2012-07-24 07:45:54 +08:00
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V2 = RegInfo.createVirtualRegister(RC);
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2012-02-25 06:34:47 +08:00
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if (Subtarget.isABI_N64()) {
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MF.getRegInfo().addLiveIn(Mips::T9_64);
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2012-03-27 10:46:25 +08:00
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MBB.addLiveIn(Mips::T9_64);
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2012-02-25 06:34:47 +08:00
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// daddu $v1, $v0, $t9
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// daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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2012-06-15 05:10:56 +08:00
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BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
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.addReg(Mips::T9_64);
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2012-02-25 06:34:47 +08:00
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BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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2012-05-12 08:17:17 +08:00
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return;
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}
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2012-07-24 07:45:54 +08:00
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if (Subtarget.inMips16Mode()) {
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BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
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2012-07-25 11:16:47 +08:00
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.addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
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.addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
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BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
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2012-07-24 07:45:54 +08:00
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BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
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.addReg(V1).addReg(V2);
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return;
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}
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2012-05-12 08:17:17 +08:00
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if (MF.getTarget().getRelocationModel() == Reloc::Static) {
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2012-02-25 06:34:47 +08:00
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// Set global register to __gnu_local_gp.
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//
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// lui $v0, %hi(__gnu_local_gp)
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// addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
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2012-05-12 08:17:17 +08:00
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return;
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2012-02-28 15:46:26 +08:00
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}
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2012-05-12 08:17:17 +08:00
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MF.getRegInfo().addLiveIn(Mips::T9);
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MBB.addLiveIn(Mips::T9);
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if (Subtarget.isABI_N32()) {
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// addu $v1, $v0, $t9
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// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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assert(Subtarget.isABI_O32());
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// For O32 ABI, the following instruction sequence is emitted to initialize
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// the global base register:
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//
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// 0. lui $2, %hi(_gp_disp)
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// 1. addiu $2, $2, %lo(_gp_disp)
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// 2. addu $globalbasereg, $2, $t9
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//
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// We emit only the last instruction here.
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//
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// GNU linker requires that the first two instructions appear at the beginning
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2012-06-02 18:20:22 +08:00
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// of a function and no instructions be inserted before or between them.
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2012-05-12 08:17:17 +08:00
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// The two instructions are emitted during lowering to MC layer in order to
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// avoid any reordering.
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//
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// Register $2 (Mips::V0) is added to the list of live-in registers to ensure
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// the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
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// reads it.
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MF.getRegInfo().addLiveIn(Mips::V0);
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MBB.addLiveIn(Mips::V0);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
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.addReg(Mips::V0).addReg(Mips::T9);
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2012-02-25 06:34:47 +08:00
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}
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2012-10-28 14:02:37 +08:00
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// Insert instructions to initialize the Mips16 SP Alias register in the
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// first MBB of the function.
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//
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void MipsDAGToDAGISel::InitMips16SPAliasReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->mips16SPAliasRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
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|
|
BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
|
|
|
|
.addReg(Mips::SP);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-03-08 09:51:59 +08:00
|
|
|
bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
|
|
|
|
const MachineInstr& MI) {
|
|
|
|
unsigned DstReg = 0, ZeroReg = 0;
|
|
|
|
|
|
|
|
// Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
|
|
|
|
if ((MI.getOpcode() == Mips::ADDiu) &&
|
|
|
|
(MI.getOperand(1).getReg() == Mips::ZERO) &&
|
|
|
|
(MI.getOperand(2).getImm() == 0)) {
|
|
|
|
DstReg = MI.getOperand(0).getReg();
|
|
|
|
ZeroReg = Mips::ZERO;
|
|
|
|
} else if ((MI.getOpcode() == Mips::DADDiu) &&
|
|
|
|
(MI.getOperand(1).getReg() == Mips::ZERO_64) &&
|
|
|
|
(MI.getOperand(2).getImm() == 0)) {
|
|
|
|
DstReg = MI.getOperand(0).getReg();
|
|
|
|
ZeroReg = Mips::ZERO_64;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!DstReg)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Replace uses with ZeroReg.
|
|
|
|
for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
|
2012-08-10 06:08:24 +08:00
|
|
|
E = MRI->use_end(); U != E;) {
|
2012-03-08 09:51:59 +08:00
|
|
|
MachineOperand &MO = U.getOperand();
|
2012-08-10 06:08:24 +08:00
|
|
|
unsigned OpNo = U.getOperandNo();
|
2012-03-08 09:51:59 +08:00
|
|
|
MachineInstr *MI = MO.getParent();
|
2012-08-10 06:08:24 +08:00
|
|
|
++U;
|
2012-03-08 09:51:59 +08:00
|
|
|
|
|
|
|
// Do not replace if it is a phi's operand or is tied to def operand.
|
2012-08-10 06:08:24 +08:00
|
|
|
if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
|
2012-03-08 09:51:59 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
MO.setReg(ZeroReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
|
|
|
|
InitGlobalBaseReg(MF);
|
2012-10-28 14:02:37 +08:00
|
|
|
InitMips16SPAliasReg(MF);
|
2012-03-08 09:51:59 +08:00
|
|
|
|
|
|
|
MachineRegisterInfo *MRI = &MF.getRegInfo();
|
|
|
|
|
|
|
|
for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
|
|
|
|
++MFI)
|
|
|
|
for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
|
|
|
|
ReplaceUsesWithZeroReg(MRI, *I);
|
|
|
|
}
|
|
|
|
|
2012-02-25 06:34:47 +08:00
|
|
|
bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
|
2012-02-28 15:46:26 +08:00
|
|
|
|
2012-03-08 09:51:59 +08:00
|
|
|
ProcessFunctionAfterISel(MF);
|
2012-02-25 06:34:47 +08:00
|
|
|
|
|
|
|
return Ret;
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2007-11-13 03:49:57 +08:00
|
|
|
/// getGlobalBaseReg - Output the instructions required to put the
|
|
|
|
/// GOT address into a register.
|
2009-06-04 04:30:14 +08:00
|
|
|
SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
|
2012-02-25 06:34:47 +08:00
|
|
|
unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
|
2009-06-04 04:30:14 +08:00
|
|
|
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
|
2007-11-13 03:49:57 +08:00
|
|
|
}
|
|
|
|
|
2012-10-28 14:02:37 +08:00
|
|
|
/// getMips16SPAliasReg - Output the instructions required to put the
|
|
|
|
/// SP into a Mips16 accessible aliased register.
|
|
|
|
SDValue MipsDAGToDAGISel::getMips16SPAliasReg() {
|
|
|
|
unsigned Mips16SPAliasReg =
|
|
|
|
MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
|
|
|
|
return CurDAG->getRegister(Mips16SPAliasReg, TLI.getPointerTy());
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
/// ComplexPattern used on MipsInstrInfo
|
|
|
|
/// Used on Mips Load/Store instructions
|
2013-02-16 08:14:37 +08:00
|
|
|
bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
2011-10-11 08:44:20 +08:00
|
|
|
EVT ValTy = Addr.getValueType();
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// if Address is FI, get the TargetFrameIndex.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
2011-10-11 08:44:20 +08:00
|
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
|
|
|
|
Offset = CurDAG->getTargetConstant(0, ValTy);
|
2007-06-06 15:42:06 +08:00
|
|
|
return true;
|
|
|
|
}
|
2011-03-05 01:51:39 +08:00
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
// on PIC code Load GA
|
2011-12-09 09:53:17 +08:00
|
|
|
if (Addr.getOpcode() == MipsISD::Wrapper) {
|
2012-02-25 06:34:47 +08:00
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
Offset = Addr.getOperand(1);
|
2011-12-09 04:34:32 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (TM.getRelocationModel() != Reloc::PIC_) {
|
2008-09-17 05:48:12 +08:00
|
|
|
if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
2007-11-05 11:02:32 +08:00
|
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress))
|
|
|
|
return false;
|
2011-03-05 01:51:39 +08:00
|
|
|
}
|
|
|
|
|
2011-06-02 09:03:14 +08:00
|
|
|
// Addresses of the form FI+const or FI|const
|
|
|
|
if (CurDAG->isBaseWithConstantOffset(Addr)) {
|
|
|
|
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
|
|
|
|
if (isInt<16>(CN->getSExtValue())) {
|
|
|
|
|
|
|
|
// If the first operand is a FI, get the TargetFI Node
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
|
|
|
|
(Addr.getOperand(0)))
|
2011-10-11 08:44:20 +08:00
|
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
|
2011-06-02 09:03:14 +08:00
|
|
|
else
|
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
|
2011-10-11 08:44:20 +08:00
|
|
|
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
|
2011-06-02 09:03:14 +08:00
|
|
|
return true;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2011-06-02 09:03:14 +08:00
|
|
|
}
|
2009-11-16 12:33:42 +08:00
|
|
|
|
2011-06-02 09:03:14 +08:00
|
|
|
// Operand is a result from an ADD.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
2009-11-16 12:33:42 +08:00
|
|
|
// When loading from constant pools, load the lower address part in
|
2009-11-25 20:17:58 +08:00
|
|
|
// the instruction itself. Example, instead of:
|
2009-11-16 12:33:42 +08:00
|
|
|
// lui $2, %hi($CPI1_0)
|
|
|
|
// addiu $2, $2, %lo($CPI1_0)
|
|
|
|
// lwc1 $f0, 0($2)
|
|
|
|
// Generate:
|
|
|
|
// lui $2, %hi($CPI1_0)
|
|
|
|
// lwc1 $f0, %lo($CPI1_0)($2)
|
2012-08-25 04:21:49 +08:00
|
|
|
if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
|
|
|
|
Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
|
|
|
|
SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
|
2012-06-14 04:33:18 +08:00
|
|
|
if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
|
|
|
|
isa<JumpTableSDNode>(Opnd0)) {
|
2009-11-25 20:17:58 +08:00
|
|
|
Base = Addr.getOperand(0);
|
2012-06-14 04:33:18 +08:00
|
|
|
Offset = Opnd0;
|
2009-11-25 20:17:58 +08:00
|
|
|
return true;
|
2009-11-16 12:33:42 +08:00
|
|
|
}
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
2013-02-16 05:20:45 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-02-16 08:14:37 +08:00
|
|
|
bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
2013-02-16 05:20:45 +08:00
|
|
|
Base = Addr;
|
|
|
|
Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
|
2007-06-06 15:42:06 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-02-16 08:14:37 +08:00
|
|
|
bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
return selectAddrRegImm(Addr, Base, Offset) ||
|
|
|
|
selectAddrDefault(Addr, Base, Offset);
|
2013-02-16 05:20:45 +08:00
|
|
|
}
|
|
|
|
|
2012-10-28 14:02:37 +08:00
|
|
|
void MipsDAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
|
|
|
|
SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, TLI.getPointerTy());
|
|
|
|
if (Parent) {
|
|
|
|
switch (Parent->getOpcode()) {
|
|
|
|
case ISD::LOAD: {
|
|
|
|
LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
|
|
|
|
switch (SD->getMemoryVT().getSizeInBits()) {
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
AliasReg = TM.getFrameLowering()->hasFP(*MF)?
|
|
|
|
AliasFPReg: getMips16SPAliasReg();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::STORE: {
|
|
|
|
StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
|
|
|
|
switch (SD->getMemoryVT().getSizeInBits()) {
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
AliasReg = TM.getFrameLowering()->hasFP(*MF)?
|
|
|
|
AliasFPReg: getMips16SPAliasReg();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
AliasReg = CurDAG->getRegister(Mips::SP, TLI.getPointerTy());
|
|
|
|
return;
|
|
|
|
|
|
|
|
}
|
|
|
|
bool MipsDAGToDAGISel::SelectAddr16(
|
|
|
|
SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
|
|
|
|
SDValue &Alias) {
|
|
|
|
EVT ValTy = Addr.getValueType();
|
|
|
|
|
|
|
|
Alias = CurDAG->getTargetConstant(0, ValTy);
|
|
|
|
|
|
|
|
// if Address is FI, get the TargetFrameIndex.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
|
|
|
|
Offset = CurDAG->getTargetConstant(0, ValTy);
|
|
|
|
getMips16SPRefReg(Parent, Alias);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
// on PIC code Load GA
|
|
|
|
if (Addr.getOpcode() == MipsISD::Wrapper) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
Offset = Addr.getOperand(1);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (TM.getRelocationModel() != Reloc::PIC_) {
|
|
|
|
if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// Addresses of the form FI+const or FI|const
|
|
|
|
if (CurDAG->isBaseWithConstantOffset(Addr)) {
|
|
|
|
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
|
|
|
|
if (isInt<16>(CN->getSExtValue())) {
|
|
|
|
|
|
|
|
// If the first operand is a FI, get the TargetFI Node
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
|
|
|
|
(Addr.getOperand(0))) {
|
|
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
|
|
|
|
getMips16SPRefReg(Parent, Alias);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
|
|
|
|
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Operand is a result from an ADD.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
|
|
// When loading from constant pools, load the lower address part in
|
|
|
|
// the instruction itself. Example, instead of:
|
|
|
|
// lui $2, %hi($CPI1_0)
|
|
|
|
// addiu $2, $2, %lo($CPI1_0)
|
|
|
|
// lwc1 $f0, 0($2)
|
|
|
|
// Generate:
|
|
|
|
// lui $2, %hi($CPI1_0)
|
|
|
|
// lwc1 $f0, %lo($CPI1_0)($2)
|
|
|
|
if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
|
|
|
|
Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
|
|
|
|
SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
|
|
|
|
if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
|
|
|
|
isa<JumpTableSDNode>(Opnd0)) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
Offset = Opnd0;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If an indexed floating point load/store can be emitted, return false.
|
|
|
|
const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
|
|
|
|
|
|
|
|
if (LS &&
|
|
|
|
(LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
|
2012-11-16 05:17:13 +08:00
|
|
|
Subtarget.hasFPIdx())
|
2012-10-28 14:02:37 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
Base = Addr;
|
|
|
|
Offset = CurDAG->getTargetConstant(0, ValTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-12-21 07:10:57 +08:00
|
|
|
/// Select multiply instructions.
|
|
|
|
std::pair<SDNode*, SDNode*>
|
2012-02-28 15:46:26 +08:00
|
|
|
MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
|
2011-12-21 07:10:57 +08:00
|
|
|
bool HasLo, bool HasHi) {
|
2012-01-07 04:02:49 +08:00
|
|
|
SDNode *Lo = 0, *Hi = 0;
|
2011-12-21 07:10:57 +08:00
|
|
|
SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
|
|
|
|
N->getOperand(1));
|
|
|
|
SDValue InFlag = SDValue(Mul, 0);
|
|
|
|
|
|
|
|
if (HasLo) {
|
2012-10-06 02:27:54 +08:00
|
|
|
unsigned Opcode = Subtarget.inMips16Mode() ? Mips::Mflo16 :
|
|
|
|
(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
|
|
|
|
Lo = CurDAG->getMachineNode(Opcode, dl, Ty, MVT::Glue, InFlag);
|
2011-12-21 07:10:57 +08:00
|
|
|
InFlag = SDValue(Lo, 1);
|
|
|
|
}
|
2012-10-06 02:27:54 +08:00
|
|
|
if (HasHi) {
|
|
|
|
unsigned Opcode = Subtarget.inMips16Mode() ? Mips::Mfhi16 :
|
|
|
|
(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64);
|
|
|
|
Hi = CurDAG->getMachineNode(Opcode, dl, Ty, InFlag);
|
|
|
|
}
|
2011-12-21 07:10:57 +08:00
|
|
|
return std::make_pair(Lo, Hi);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
/// Select instructions not customized! Used for
|
|
|
|
/// expanded, promoted and normal instructions
|
2010-01-05 09:24:18 +08:00
|
|
|
SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
2007-06-06 15:42:06 +08:00
|
|
|
unsigned Opcode = Node->getOpcode();
|
2009-02-05 07:02:30 +08:00
|
|
|
DebugLoc dl = Node->getDebugLoc();
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Dump information about the Node being selected
|
2010-03-02 14:34:30 +08:00
|
|
|
DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// If we have a custom node, we already have selected!
|
2008-07-18 03:10:17 +08:00
|
|
|
if (Node->isMachineOpcode()) {
|
2010-03-02 14:34:30 +08:00
|
|
|
DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
|
2007-06-06 15:42:06 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
///
|
2011-03-05 01:51:39 +08:00
|
|
|
// Instruction Selection not handled by the auto-generated
|
2007-09-25 04:15:11 +08:00
|
|
|
// tablegen selection should be handled here.
|
2011-03-05 01:51:39 +08:00
|
|
|
///
|
2011-12-21 07:10:57 +08:00
|
|
|
EVT NodeTy = Node->getValueType(0);
|
|
|
|
unsigned MultOpc;
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
switch(Opcode) {
|
2011-12-21 06:58:01 +08:00
|
|
|
default: break;
|
|
|
|
|
|
|
|
case ISD::SUBE:
|
|
|
|
case ISD::ADDE: {
|
2012-10-26 12:46:26 +08:00
|
|
|
bool inMips16Mode = Subtarget.inMips16Mode();
|
2011-12-21 06:58:01 +08:00
|
|
|
SDValue InFlag = Node->getOperand(2), CmpLHS;
|
|
|
|
unsigned Opc = InFlag.getOpcode(); (void)Opc;
|
|
|
|
assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
|
|
|
|
(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
|
|
|
"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
|
|
|
|
|
|
|
|
unsigned MOp;
|
|
|
|
if (Opcode == ISD::ADDE) {
|
|
|
|
CmpLHS = InFlag.getValue(0);
|
2012-10-26 12:46:26 +08:00
|
|
|
if (inMips16Mode)
|
|
|
|
MOp = Mips::AdduRxRyRz16;
|
|
|
|
else
|
|
|
|
MOp = Mips::ADDu;
|
2011-12-21 06:58:01 +08:00
|
|
|
} else {
|
|
|
|
CmpLHS = InFlag.getOperand(0);
|
2012-10-26 12:46:26 +08:00
|
|
|
if (inMips16Mode)
|
|
|
|
MOp = Mips::SubuRxRyRz16;
|
|
|
|
else
|
|
|
|
MOp = Mips::SUBu;
|
2011-12-21 06:58:01 +08:00
|
|
|
}
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
SDValue LHS = Node->getOperand(0);
|
|
|
|
SDValue RHS = Node->getOperand(1);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
EVT VT = LHS.getValueType();
|
2012-10-26 12:46:26 +08:00
|
|
|
|
|
|
|
unsigned Sltu_op = inMips16Mode? Mips::SltuRxRyRz16: Mips::SLTu;
|
|
|
|
SDNode *Carry = CurDAG->getMachineNode(Sltu_op, dl, VT, Ops, 2);
|
|
|
|
unsigned Addu_op = inMips16Mode? Mips::AdduRxRyRz16 : Mips::ADDu;
|
|
|
|
SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, dl, VT,
|
2011-12-21 06:58:01 +08:00
|
|
|
SDValue(Carry,0), RHS);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
|
|
|
|
LHS, SDValue(AddCarry,0));
|
|
|
|
}
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
/// Mul with two results
|
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI: {
|
2012-10-06 02:27:54 +08:00
|
|
|
if (NodeTy == MVT::i32) {
|
|
|
|
if (Subtarget.inMips16Mode())
|
|
|
|
MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 :
|
|
|
|
Mips::MultRxRy16);
|
|
|
|
else
|
|
|
|
MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
|
|
|
|
}
|
2011-12-21 07:10:57 +08:00
|
|
|
else
|
|
|
|
MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2011-12-21 07:10:57 +08:00
|
|
|
std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
|
|
|
|
true, true);
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
if (!SDValue(Node, 0).use_empty())
|
2011-12-21 07:10:57 +08:00
|
|
|
ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
if (!SDValue(Node, 1).use_empty())
|
2011-12-21 07:10:57 +08:00
|
|
|
ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
|
2008-06-06 14:37:31 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
2008-06-06 08:58:26 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
/// Special Muls
|
2011-12-21 07:10:57 +08:00
|
|
|
case ISD::MUL: {
|
2011-12-21 06:58:01 +08:00
|
|
|
// Mips32 has a 32-bit three operand mul instruction.
|
2011-12-21 07:10:57 +08:00
|
|
|
if (Subtarget.hasMips32() && NodeTy == MVT::i32)
|
2011-12-21 06:58:01 +08:00
|
|
|
break;
|
2011-12-21 07:10:57 +08:00
|
|
|
return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
|
|
|
|
dl, NodeTy, true, false).first;
|
|
|
|
}
|
2011-12-21 06:58:01 +08:00
|
|
|
case ISD::MULHS:
|
|
|
|
case ISD::MULHU: {
|
2012-10-06 02:27:54 +08:00
|
|
|
if (NodeTy == MVT::i32) {
|
|
|
|
if (Subtarget.inMips16Mode())
|
|
|
|
MultOpc = (Opcode == ISD::MULHU ?
|
|
|
|
Mips::MultuRxRy16 : Mips::MultRxRy16);
|
|
|
|
else
|
|
|
|
MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
|
|
|
|
}
|
2011-12-21 06:58:01 +08:00
|
|
|
else
|
2011-12-21 07:10:57 +08:00
|
|
|
MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
|
|
|
|
|
|
|
|
return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
|
2011-12-21 06:58:01 +08:00
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
// Get target GOT address.
|
|
|
|
case ISD::GLOBAL_OFFSET_TABLE:
|
|
|
|
return getGlobalBaseReg();
|
2011-12-21 06:25:50 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
case ISD::ConstantFP: {
|
|
|
|
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
|
|
|
|
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
|
|
|
|
if (Subtarget.hasMips64()) {
|
2011-03-05 01:51:39 +08:00
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
2011-12-21 06:58:01 +08:00
|
|
|
Mips::ZERO_64, MVT::i64);
|
|
|
|
return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
|
2009-11-14 02:49:59 +08:00
|
|
|
}
|
2011-12-21 06:58:01 +08:00
|
|
|
|
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
Mips::ZERO, MVT::i32);
|
|
|
|
return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
|
|
|
|
Zero);
|
2009-11-14 02:49:59 +08:00
|
|
|
}
|
2011-12-21 06:58:01 +08:00
|
|
|
break;
|
|
|
|
}
|
2009-11-14 02:49:59 +08:00
|
|
|
|
2012-01-25 11:01:35 +08:00
|
|
|
case ISD::Constant: {
|
|
|
|
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
|
|
|
|
unsigned Size = CN->getValueSizeInBits(0);
|
|
|
|
|
|
|
|
if (Size == 32)
|
|
|
|
break;
|
|
|
|
|
|
|
|
MipsAnalyzeImmediate AnalyzeImm;
|
|
|
|
int64_t Imm = CN->getSExtValue();
|
|
|
|
|
|
|
|
const MipsAnalyzeImmediate::InstSeq &Seq =
|
|
|
|
AnalyzeImm.Analyze(Imm, Size, false);
|
2012-02-28 15:46:26 +08:00
|
|
|
|
2012-01-25 11:01:35 +08:00
|
|
|
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
|
|
|
|
DebugLoc DL = CN->getDebugLoc();
|
|
|
|
SDNode *RegOpnd;
|
|
|
|
SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
|
|
|
|
MVT::i64);
|
|
|
|
|
|
|
|
// The first instruction can be a LUi which is different from other
|
|
|
|
// instructions (ADDiu, ORI and SLL) in that it does not have a register
|
|
|
|
// operand.
|
|
|
|
if (Inst->Opc == Mips::LUi64)
|
|
|
|
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
|
|
|
|
else
|
|
|
|
RegOpnd =
|
|
|
|
CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
|
|
|
CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
|
|
|
|
ImmOpnd);
|
|
|
|
|
|
|
|
// The remaining instructions in the sequence are handled here.
|
|
|
|
for (++Inst; Inst != Seq.end(); ++Inst) {
|
|
|
|
ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
|
|
|
|
MVT::i64);
|
|
|
|
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
|
|
|
SDValue(RegOpnd, 0), ImmOpnd);
|
|
|
|
}
|
|
|
|
|
|
|
|
return RegOpnd;
|
|
|
|
}
|
|
|
|
|
2012-09-15 09:52:08 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
case ISD::LOAD:
|
|
|
|
case ISD::STORE:
|
|
|
|
assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
|
|
|
|
cast<MemSDNode>(Node)->getAlignment() &&
|
|
|
|
"Unexpected unaligned loads/stores.");
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
case MipsISD::ThreadPointer: {
|
|
|
|
EVT PtrVT = TLI.getPointerTy();
|
|
|
|
unsigned RdhwrOpc, SrcReg, DestReg;
|
|
|
|
|
|
|
|
if (PtrVT == MVT::i32) {
|
|
|
|
RdhwrOpc = Mips::RDHWR;
|
|
|
|
SrcReg = Mips::HWR29;
|
|
|
|
DestReg = Mips::V1;
|
|
|
|
} else {
|
|
|
|
RdhwrOpc = Mips::RDHWR64;
|
|
|
|
SrcReg = Mips::HWR29_64;
|
|
|
|
DestReg = Mips::V1_64;
|
2011-05-31 10:53:58 +08:00
|
|
|
}
|
2012-02-28 15:46:26 +08:00
|
|
|
|
2011-12-21 06:58:01 +08:00
|
|
|
SDNode *Rdhwr =
|
|
|
|
CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
|
|
|
|
Node->getValueType(0),
|
|
|
|
CurDAG->getRegister(SrcReg, PtrVT));
|
|
|
|
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
|
|
|
|
SDValue(Rdhwr, 0));
|
|
|
|
SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
|
|
|
|
ReplaceUses(SDValue(Node, 0), ResNode);
|
|
|
|
return ResNode.getNode();
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Select the default instruction
|
2010-01-05 09:24:18 +08:00
|
|
|
SDNode *ResNode = SelectCode(Node);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2010-03-02 14:34:30 +08:00
|
|
|
DEBUG(errs() << "=> ");
|
2010-01-05 09:24:18 +08:00
|
|
|
if (ResNode == NULL || ResNode == Node)
|
|
|
|
DEBUG(Node->dump(CurDAG));
|
2007-06-06 15:42:06 +08:00
|
|
|
else
|
|
|
|
DEBUG(ResNode->dump(CurDAG));
|
2009-08-23 14:49:22 +08:00
|
|
|
DEBUG(errs() << "\n");
|
2007-06-06 15:42:06 +08:00
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
2011-06-21 08:40:49 +08:00
|
|
|
bool MipsDAGToDAGISel::
|
|
|
|
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
|
|
|
std::vector<SDValue> &OutOps) {
|
|
|
|
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
|
|
|
|
OutOps.push_back(Op);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-03-05 01:51:39 +08:00
|
|
|
/// createMipsISelDag - This pass converts a legalized DAG into a
|
2007-06-06 15:42:06 +08:00
|
|
|
/// MIPS-specific DAG, ready for instruction scheduling.
|
|
|
|
FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
|
|
|
|
return new MipsDAGToDAGISel(TM);
|
|
|
|
}
|