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llvm-project/llvm/test/CodeGen/X86/widen_arith-2.ll

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[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
2017-06-19 05:30:57 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s
Added some basic test cases for r61209 llvm-svn: 61210
2008-12-19 04:05:58 +08:00
; widen v8i8 to v16i8 (checks even power of 2 widening with add & and)
define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind {
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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; CHECK-LABEL: update:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movl $0, (%esp)
[x86] transform vector inc/dec to use -1 constant (PR33483) Convert vector increment or decrement to sub/add with an all-ones constant: add X, <1, 1...> --> sub X, <-1, -1...> sub X, <1, 1...> --> add X, <-1, -1...> The all-ones vector constant can be materialized using a pcmpeq instruction that is commonly recognized as an idiom (has no register dependency), so that's better than loading a splat 1 constant. AVX512 uses 'vpternlogd' for 512-bit vectors because there is apparently no better way to produce 512 one-bits. The general advantages of this lowering are: 1. pcmpeq has lower latency than a memop on every uarch I looked at in Agner's tables, so in theory, this could be better for perf, but... 2. That seems unlikely to affect any OOO implementation, and I can't measure any real perf difference from this transform on Haswell or Jaguar, but... 3. It doesn't look like it from the diffs, but this is an overall size win because we eliminate 16 - 64 constant bytes in the case of a vector load. If we're broadcasting a scalar load (which might itself be a bug), then we're replacing a scalar constant load + broadcast with a single cheap op, so that should always be smaller/better too. 4. This makes the DAG/isel output more consistent - we use pcmpeq already for padd x, -1 and psub x, -1, so we should use that form for +1 too because we can. If there's some reason to favor a constant load on some CPU, let's make the reverse transform for all of these cases (either here in the DAG or in a later machine pass). This should fix: https://bugs.llvm.org/show_bug.cgi?id=33483 Differential Revision: https://reviews.llvm.org/D34336 llvm-svn: 306289
2017-06-26 22:19:26 +08:00
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
2017-06-19 05:30:57 +08:00
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4]
; CHECK-NEXT: jmp .LBB0_1
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %forbody
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: movl (%esp), %eax
[DAG] Improve Aliasing of operations to static alloca Re-recommiting after landing DAG extension-crash fix. Recommiting after adding check to avoid miscomputing alias information on addresses of the same base but different subindices. Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 308350
2017-07-19 04:06:24 +08:00
; CHECK-NEXT: leal (,%eax,8), %ecx
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
2017-06-19 05:30:57 +08:00
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
[DAG] Improve Aliasing of operations to static alloca Re-recommiting after landing DAG extension-crash fix. Recommiting after adding check to avoid miscomputing alias information on addresses of the same base but different subindices. Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 308350
2017-07-19 04:06:24 +08:00
; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles. Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773 Differential Revision: https://reviews.llvm.org/D38472 llvm-svn: 314788
2017-10-03 20:01:31 +08:00
; CHECK-NEXT: pmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; CHECK-NEXT: psubw %xmm0, %xmm2
; CHECK-NEXT: pand %xmm1, %xmm2
[X86][SSE] Consistently prefer lowering to PACKUS over PACKSS We have some combines/lowerings that attempt to use PACKSS-then-PACKUS and others that use PACKUS-then-PACKSS. PACKUS is much easier to combine with if we know the upper bits are zero as ComputeKnownBits can easily see through BITCASTs etc. especially now that rL333995 and rL334007 have landed. It also effectively works at byte level which further simplifies shuffle combines. The only (minor) annoyances are that ComputeKnownBits can sometimes take longer as it doesn't fail as quickly as ComputeNumSignBits (but I'm not seeing any actual regressions in tests) and PACKUSDW only became available after SSE41 so we have more codegen diffs between targets. llvm-svn: 334276
2018-06-08 18:29:00 +08:00
; CHECK-NEXT: packuswb %xmm0, %xmm2
[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles. Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773 Differential Revision: https://reviews.llvm.org/D38472 llvm-svn: 314788
2017-10-03 20:01:31 +08:00
; CHECK-NEXT: movq %xmm2, (%edx,%eax,8)
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
2017-06-19 05:30:57 +08:00
; CHECK-NEXT: incl (%esp)
; CHECK-NEXT: .LBB0_1: # %forcond
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl (%esp), %eax
; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: jl .LBB0_2
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: # %bb.3: # %afterfor
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
2017-06-19 05:30:57 +08:00
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
Added some basic test cases for r61209 llvm-svn: 61210
2008-12-19 04:05:58 +08:00
entry:
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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%dst_i.addr = alloca i64*
%src_i.addr = alloca i64*
%n.addr = alloca i32
%i = alloca i32, align 4
%dst = alloca <8 x i8>*, align 4
%src = alloca <8 x i8>*, align 4
Added some basic test cases for r61209 llvm-svn: 61210
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store i64* %dst_i, i64** %dst_i.addr
store i64* %src_i, i64** %src_i.addr
store i32 %n, i32* %n.addr
store i32 0, i32* %i
br label %forcond
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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forcond:
%tmp = load i32, i32* %i
%tmp1 = load i32, i32* %n.addr
%cmp = icmp slt i32 %tmp, %tmp1
Added some basic test cases for r61209 llvm-svn: 61210
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br i1 %cmp, label %forbody, label %afterfor
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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forbody:
%tmp2 = load i32, i32* %i
%tmp3 = load i64*, i64** %dst_i.addr
%arrayidx = getelementptr i64, i64* %tmp3, i32 %tmp2
%conv = bitcast i64* %arrayidx to <8 x i8>*
Added some basic test cases for r61209 llvm-svn: 61210
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store <8 x i8>* %conv, <8 x i8>** %dst
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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%tmp4 = load i32, i32* %i
%tmp5 = load i64*, i64** %src_i.addr
%arrayidx6 = getelementptr i64, i64* %tmp5, i32 %tmp4
%conv7 = bitcast i64* %arrayidx6 to <8 x i8>*
Added some basic test cases for r61209 llvm-svn: 61210
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store <8 x i8>* %conv7, <8 x i8>** %src
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
2017-06-19 05:30:57 +08:00
%tmp8 = load i32, i32* %i
%tmp9 = load <8 x i8>*, <8 x i8>** %dst
%arrayidx10 = getelementptr <8 x i8>, <8 x i8>* %tmp9, i32 %tmp8
%tmp11 = load i32, i32* %i
%tmp12 = load <8 x i8>*, <8 x i8>** %src
%arrayidx13 = getelementptr <8 x i8>, <8 x i8>* %tmp12, i32 %tmp11
%tmp14 = load <8 x i8>, <8 x i8>* %arrayidx13
%add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 >
%and = and <8 x i8> %add, < i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4 >
Added some basic test cases for r61209 llvm-svn: 61210
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store <8 x i8> %and, <8 x i8>* %arrayidx10
br label %forinc
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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forinc:
%tmp15 = load i32, i32* %i
%inc = add i32 %tmp15, 1
Added some basic test cases for r61209 llvm-svn: 61210
2008-12-19 04:05:58 +08:00
store i32 %inc, i32* %i
br label %forcond
[x86] specify triple and auto-generate checks; NFC llvm-svn: 305654
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afterfor:
Added some basic test cases for r61209 llvm-svn: 61210
2008-12-19 04:05:58 +08:00
ret void
}