llvm-project/llvm/test/CodeGen/X86/fast-cc-pass-in-regs.ll

; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
; RUN:   grep {mov	EDX, 1}
; check that fastcc is passing stuff in regs.

declare x86_fastcallcc i64 @callee(i64)

define i64 @caller() {
        %X = call x86_fastcallcc  i64 @callee( i64 4294967299 )          ; <i64> [#uses=1]
        ret i64 %X
}

define x86_fastcallcc i64 @caller2(i64 %X) {
        ret i64 %X
}
For PR1319: Upgrade to new test harness. llvm-svn: 36091 2007-04-16 06:20:47 +08:00			`; RUN: llvm-as < %s \| llc -march=x86 -x86-asm-syntax=intel \| \`
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648 2007-08-01 04:11:57 +08:00			`; RUN: grep {mov EDX, 1}`
reg test llvm-svn: 21914 2005-05-13 07:09:04 +08:00			`; check that fastcc is passing stuff in regs.`

fastcc -> fastcall llvm-svn: 34749 2007-03-01 02:35:36 +08:00			`declare x86_fastcallcc i64 @callee(i64)`
update testcases for x86 fastcc changes. llvm-svn: 26842 2006-03-19 07:48:54 +08:00
fastcc -> fastcall llvm-svn: 34749 2007-03-01 02:35:36 +08:00			`define i64 @caller() {`
fix bogus test that the more strict lexer is finding. llvm-svn: 44216 2007-11-19 02:26:45 +08:00			`%X = call x86_fastcallcc i64 @callee( i64 4294967299 ) ; <i64> [#uses=1]`
fastcc -> fastcall llvm-svn: 34749 2007-03-01 02:35:36 +08:00			`ret i64 %X`
reg test llvm-svn: 21914 2005-05-13 07:09:04 +08:00			`}`

fastcc -> fastcall llvm-svn: 34749 2007-03-01 02:35:36 +08:00			`define x86_fastcallcc i64 @caller2(i64 %X) {`
			`ret i64 %X`
reg test llvm-svn: 21914 2005-05-13 07:09:04 +08:00			`}`
fastcc -> fastcall llvm-svn: 34749 2007-03-01 02:35:36 +08:00