maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll

99 lines
6.2 KiB
LLVM
Raw Normal View History

Eliminate more linear scan tests. llvm-svn: 144462
2011-11-13 04:35:26 +08:00
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=basic | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -regalloc=basic | FileCheck %s
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
Make physreg coalescing independent on the number of uses of the virtual register. The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
2011-03-10 03:27:06 +08:00
; This testcase should need to spill the -1 value on both x86-32 and x86-64,
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
; so it shouldn't use pcmpeqd to materialize an all-ones vector; it
; should use a constant-pool load instead.
Eliminate more linear scan tests. llvm-svn: 144462
2011-11-13 04:35:26 +08:00
;
; RAGreedy defeats the test by splitting live ranges.
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
Make physreg coalescing independent on the number of uses of the virtual register. The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
2011-03-10 03:27:06 +08:00
; Constant pool all-ones vector:
Chris's constant data sequence refactoring actually enabled printing vectors of all one bits to be printed more cleverly in the AsmPrinter. Unfortunately, the byte value for all one bits is the same with -fsigned-char as the error return of '-1'. Force this to be the unsigned byte value when returning it to avoid this problem, and update the test case for the shiny new behavior. Yay for building LLVM and Clang with -funsigned-char. Chris, please review, and let me know if there is any reason to not desire this change. It seems good on the surface, and certainly intended based on the code written. llvm-svn: 149299
2012-01-31 07:47:44 +08:00
; CHECK: .space 16,255
Make physreg coalescing independent on the number of uses of the virtual register. The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
2011-03-10 03:27:06 +08:00
; No pcmpeqd instructions, everybody uses the constant pool.
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: program_1:
Make physreg coalescing independent on the number of uses of the virtual register. The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
2011-03-10 03:27:06 +08:00
; CHECK-NOT: pcmpeqd
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
%struct._cl_image_format_t = type <{ i32, i32, i32 }>
%struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }>
define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x float> %p0, <4 x float> %p1, <4 x float> %p4, <4 x float> %p5, <4 x float> %p6) nounwind {
entry:
%tmp3.i = load i32* null ; <i32> [#uses=1]
%cmp = icmp slt i32 0, %tmp3.i ; <i1> [#uses=1]
br i1 %cmp, label %forcond, label %ifthen
ifthen: ; preds = %entry
ret void
forcond: ; preds = %entry
%tmp3.i536 = load i32* null ; <i32> [#uses=1]
%cmp12 = icmp slt i32 0, %tmp3.i536 ; <i1> [#uses=1]
br i1 %cmp12, label %forbody, label %afterfor
forbody: ; preds = %forcond
%bitcast204.i104 = bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>> [#uses=1]
%tmp78 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> < float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02 >, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=2]
%tmp79 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp78) nounwind ; <<4 x i32>> [#uses=1]
%tmp80 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp79) nounwind ; <<4 x float>> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%sub140.i = fsub <4 x float> %tmp78, %tmp80 ; <<4 x float>> [#uses=2]
%mul166.i = fmul <4 x float> zeroinitializer, %sub140.i ; <<4 x float>> [#uses=1]
%add167.i = fadd <4 x float> %mul166.i, < float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000 > ; <<4 x float>> [#uses=1]
%mul171.i = fmul <4 x float> %add167.i, %sub140.i ; <<4 x float>> [#uses=1]
%add172.i = fadd <4 x float> %mul171.i, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast176.i = bitcast <4 x float> %add172.i to <4 x i32> ; <<4 x i32>> [#uses=1]
Teach DAG combine to handle vector add/sub with vectors of all 0s. llvm-svn: 169727
2012-12-10 16:12:29 +08:00
%andnps178.i = add <4 x i32> %bitcast176.i, <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast179.i = bitcast <4 x i32> %andnps178.i to <4 x float> ; <<4 x float>> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%mul186.i = fmul <4 x float> %bitcast179.i, zeroinitializer ; <<4 x float>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast190.i = bitcast <4 x float> %mul186.i to <4 x i32> ; <<4 x i32>> [#uses=1]
Teach DAG combine to handle vector add/sub with vectors of all 0s. llvm-svn: 169727
2012-12-10 16:12:29 +08:00
%andnps192.i = add <4 x i32> %bitcast190.i, <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%xorps.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
Teach DAG combine to handle vector logical operations with vectors of all 1s or all 0s. These cases can show up when vectors are split for legalizing. Fix some tests that were dependent on these cases not being combined. llvm-svn: 169684
2012-12-09 06:49:19 +08:00
%orps203.i = add <4 x i32> %andnps192.i, %xorps.i ; <<4 x i32>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast204.i = bitcast <4 x i32> %orps203.i to <4 x float> ; <<4 x float>> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%mul310 = fmul <4 x float> %bitcast204.i104, zeroinitializer ; <<4 x float>> [#uses=2]
%mul313 = fmul <4 x float> %bitcast204.i, zeroinitializer ; <<4 x float>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%cmpunord.i11 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i8 3) nounwind ; <<4 x float>> [#uses=1]
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
%tmp83 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul310, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
%bitcast.i3 = bitcast <4 x float> %mul310 to <4 x i32> ; <<4 x i32>> [#uses=1]
%andps.i5 = and <4 x i32> %bitcast.i3, zeroinitializer ; <<4 x i32>> [#uses=1]
call void null(<4 x float> %mul313, <4 x float> %cmpunord.i11, <4 x float> %tmp83, <4 x float> zeroinitializer, %struct.__ImageExecInfo* null, <4 x i32> zeroinitializer) nounwind
%tmp84 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul313, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast6.i13 = bitcast <4 x float> %cmpunord.i11 to <4 x i32> ; <<4 x i32>> [#uses=2]
Teach DAG combine to handle vector add/sub with vectors of all 0s. llvm-svn: 169727
2012-12-10 16:12:29 +08:00
%andps.i14 = add <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %bitcast6.i13 ; <<4 x i32>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%not.i16 = xor <4 x i32> %bitcast6.i13, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
Teach DAG combine to handle vector add/sub with vectors of all 0s. llvm-svn: 169727
2012-12-10 16:12:29 +08:00
%andnps.i17 = add <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %not.i16 ; <<4 x i32>> [#uses=1]
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%orps.i18 = or <4 x i32> %andnps.i17, %andps.i14 ; <<4 x i32>> [#uses=1]
%bitcast17.i19 = bitcast <4 x i32> %orps.i18 to <4 x float> ; <<4 x float>> [#uses=1]
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast11.i6 = bitcast <4 x float> %tmp83 to <4 x i32> ; <<4 x i32>> [#uses=1]
%not.i7 = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
%andnps.i8 = and <4 x i32> %bitcast11.i6, %not.i7 ; <<4 x i32>> [#uses=1]
%orps.i9 = or <4 x i32> %andnps.i8, %andps.i5 ; <<4 x i32>> [#uses=1]
%bitcast17.i10 = bitcast <4 x i32> %orps.i9 to <4 x float> ; <<4 x float>> [#uses=1]
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps avoid the need for spilling, add a new testcase that tests that the pcmpeqd used for V_SETALLONES is changed to a constant-pool load as needed. llvm-svn: 61831
2009-01-07 07:48:10 +08:00
%bitcast6.i = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=2]
%andps.i = and <4 x i32> zeroinitializer, %bitcast6.i ; <<4 x i32>> [#uses=1]
%bitcast11.i = bitcast <4 x float> %tmp84 to <4 x i32> ; <<4 x i32>> [#uses=1]
%not.i = xor <4 x i32> %bitcast6.i, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
%andnps.i = and <4 x i32> %bitcast11.i, %not.i ; <<4 x i32>> [#uses=1]
%orps.i = or <4 x i32> %andnps.i, %andps.i ; <<4 x i32>> [#uses=1]
%bitcast17.i = bitcast <4 x i32> %orps.i to <4 x float> ; <<4 x float>> [#uses=1]
call void null(<4 x float> %bitcast17.i19, <4 x float> %bitcast17.i10, <4 x float> %bitcast17.i, <4 x float> zeroinitializer, %struct.__ImageExecInfo* null, <4 x i32> zeroinitializer) nounwind
unreachable
afterfor: ; preds = %forcond
ret void
}
declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone
declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone