2019-06-12 23:01:36 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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2017-04-18 06:22:38 +08:00
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# RUN: llc -mtriple=x86_64-linux -run-pass=block-placement -o - %s | FileCheck %s
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---
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# check loop bb.7 is not merged with bb.10, bb.13
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# check loop bb.9 is not merged with bb.12
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name: foo
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body: |
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2019-06-12 23:01:36 +08:00
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; CHECK-LABEL: name: foo
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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|
; CHECK: TEST8ri $dl, 1, implicit-def $eflags, implicit killed $edx
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: JCC_1 %bb.1, 5, implicit $eflags
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: bb.2:
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: successors: %bb.1(0x30000000), %bb.3(0x50000000)
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
|
|
|
|
; CHECK: TEST64rr $rax, $rax, implicit-def $eflags
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: JCC_1 %bb.1, 4, implicit $eflags
|
|
|
|
; CHECK: bb.3:
|
|
|
|
; CHECK: successors: %bb.4(0x30000000), %bb.8(0x50000000)
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8)
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: JCC_1 %bb.8, 5, implicit $eflags
|
|
|
|
; CHECK: bb.4:
|
|
|
|
; CHECK: successors: %bb.1(0x30000000), %bb.5(0x50000000)
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
|
|
|
|
; CHECK: TEST64rr $rax, $rax, implicit-def $eflags
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: JCC_1 %bb.1, 4, implicit $eflags
|
|
|
|
; CHECK: bb.5 (align 4):
|
|
|
|
; CHECK: successors: %bb.6(0x71555555), %bb.8(0x0eaaaaab)
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8), (load 8)
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: JCC_1 %bb.8, 5, implicit $eflags
|
|
|
|
; CHECK: bb.6:
|
|
|
|
; CHECK: successors: %bb.1(0x04000000), %bb.5(0x7c000000)
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
|
|
|
|
; CHECK: TEST64rr $rax, $rax, implicit-def $eflags
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: JCC_1 %bb.5, 5, implicit $eflags
|
|
|
|
; CHECK: bb.1:
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
|
|
|
; CHECK: RETQ $eax
|
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
llvm-svn: 363284
2019-06-14 02:11:32 +08:00
|
|
|
; CHECK: bb.8:
|
2019-06-12 23:01:36 +08:00
|
|
|
; CHECK: $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
|
|
|
; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
|
|
|
|
; CHECK: RETQ $eax
|
2017-04-18 06:22:38 +08:00
|
|
|
bb.0:
|
|
|
|
successors: %bb.1(0x40000000), %bb.7(0x40000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
TEST8ri $dl, 1, implicit-def $eflags, implicit killed $edx
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.7, 4, implicit $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.1:
|
|
|
|
successors: %bb.16(0x80000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
JMP_1 %bb.16
|
|
|
|
|
|
|
|
bb.7:
|
|
|
|
successors: %bb.8(0x30000000), %bb.9(0x50000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
|
|
|
|
TEST64rr $rax, $rax, implicit-def $eflags
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.9, 5, implicit killed $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.8:
|
|
|
|
successors: %bb.16(0x80000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
JMP_1 %bb.16
|
|
|
|
|
|
|
|
bb.9:
|
|
|
|
successors: %bb.10(0x30000000), %bb.15(0x50000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8)
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.15, 5, implicit $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.10:
|
|
|
|
successors: %bb.11(0x30000000), %bb.12(0x50000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
|
|
|
|
TEST64rr $rax, $rax, implicit-def $eflags
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.12, 5, implicit $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.11:
|
|
|
|
successors: %bb.16(0x80000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
JMP_1 %bb.16
|
|
|
|
|
|
|
|
bb.12:
|
|
|
|
successors: %bb.13(0x71555555), %bb.15(0x0eaaaaab)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8), (load 8)
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.15, 5, implicit $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.13:
|
|
|
|
successors: %bb.14(0x04000000), %bb.12(0x7c000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
|
|
|
|
TEST64rr $rax, $rax, implicit-def $eflags
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
JCC_1 %bb.12, 5, implicit $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.14:
|
|
|
|
successors: %bb.16(0x80000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
2017-04-18 06:22:38 +08:00
|
|
|
JMP_1 %bb.16
|
|
|
|
|
|
|
|
bb.15:
|
|
|
|
successors: %bb.16(0x80000000)
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
|
|
|
|
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
bb.16:
|
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
RETQ $eax
|
2017-04-18 06:22:38 +08:00
|
|
|
|
|
|
|
...
|