2014-10-17 00:41:15 +08:00
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; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s
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[AArch64] Lower sdiv x, pow2 using add + select + shift.
The target-independent DAGcombiner will generate:
asr w1, X, #31 w1 = splat sign bit.
add X, X, w1, lsr #28 X = X + 0 or pow2-1
asr w0, X, asr #4 w0 = X/pow2
However, the add + shifts is expensive, so generate:
add w0, X, 15 w0 = X + pow2-1
cmp X, wzr X - 0
csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X;
asr w0, X, asr 4 w0 = X/pow2
llvm-svn: 213758
2014-07-23 22:57:52 +08:00
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1
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; CHECK: add w8, w0, #7
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: asr w0, w8, #3
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%div = sdiv i32 %x, 8
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ret i32 %div
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2
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; CHECK: add w8, w0, #7
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: neg w0, w8, asr #3
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%div = sdiv i32 %x, -8
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ret i32 %div
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3
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; CHECK: add w8, w0, #31
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: asr w0, w8, #5
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%div = sdiv i32 %x, 32
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ret i32 %div
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}
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define i64 @test4(i64 %x) {
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; CHECK-LABEL: test4
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; CHECK: add x8, x0, #7
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #3
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%div = sdiv i64 %x, 8
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ret i64 %div
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}
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define i64 @test5(i64 %x) {
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; CHECK-LABEL: test5
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; CHECK: add x8, x0, #7
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: neg x0, x8, asr #3
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%div = sdiv i64 %x, -8
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ret i64 %div
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}
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define i64 @test6(i64 %x) {
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; CHECK-LABEL: test6
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; CHECK: add x8, x0, #63
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #6
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%div = sdiv i64 %x, 64
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ret i64 %div
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}
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2014-10-17 00:41:15 +08:00
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define i64 @test7(i64 %x) {
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; CHECK-LABEL: test7
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; CHECK: orr [[REG:x[0-9]+]], xzr, #0xffffffffffff
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; CHECK: add x8, x0, [[REG]]
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #48
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%div = sdiv i64 %x, 281474976710656
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ret i64 %div
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}
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