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llvm-project/llvm/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; RUN: llc -O1 -march=arm64 -enable-andcmp-sinking=true < %s | FileCheck %s
; ModuleID = 'and-cbz-extr-mr.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 {
; CHECK: _foo:
entry:
%tobool = icmp eq i8* %str14, null
br i1 %tobool, label %return, label %if.end
; CHECK: %if.end
; CHECK: tbz
if.end: ; preds = %entry
%and.i.i.i = and i32 %int1, 4
%tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
land.rhs.i: ; preds = %if.end
%cmp.i.i.i = icmp eq i8* %str12, %str13
br i1 %cmp.i.i.i, label %if.then3, label %lor.rhs.i.i.i
lor.rhs.i.i.i: ; preds = %land.rhs.i
%cmp.i13.i.i.i = icmp eq i8* %str10, %str11
br i1 %cmp.i13.i.i.i, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, label %if.end5
_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds = %lor.rhs.i.i.i
%cmp.i.i.i.i = icmp eq i8* %str8, %str9
br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
if.then3: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp11 = load i8, i8* %str14, align 8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
%tmp12 = and i8 %tmp11, 2
%tmp13 = icmp ne i8 %tmp12, 0
br label %return
if.end5: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
; CHECK: %if.end5
; CHECK: tbz
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
land.rhs.i19: ; preds = %if.end5
%cmp.i.i.i18 = icmp eq i8* %str6, %str7
br i1 %cmp.i.i.i18, label %if.then7, label %lor.rhs.i.i.i23
lor.rhs.i.i.i23: ; preds = %land.rhs.i19
%cmp.i13.i.i.i22 = icmp eq i8* %str3, %str4
br i1 %cmp.i13.i.i.i22, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, label %if.end12
_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28: ; preds = %lor.rhs.i.i.i23
%cmp.i.i.i.i26 = icmp eq i8* %str1, %str2
br i1 %cmp.i.i.i.i26, label %if.then7, label %if.end12
if.then7: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %land.rhs.i19
br i1 %isTextField, label %if.then9, label %if.end12
if.then9: ; preds = %if.then7
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp23 = load i8, i8* %str5, align 8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
%tmp24 = and i8 %tmp23, 2
%tmp25 = icmp ne i8 %tmp24, 0
br label %return
if.end12: ; preds = %if.then7, %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %lor.rhs.i.i.i23, %if.end5, %if.end
%lnot = xor i1 %IsEditable, true
br label %return
return: ; preds = %if.end12, %if.then9, %if.then3, %entry
%retval.0 = phi i1 [ %tmp13, %if.then3 ], [ %tmp25, %if.then9 ], [ %lnot, %if.end12 ], [ true, %entry ]
ret i1 %retval.0
}
attributes #0 = { nounwind ssp }