2015-06-13 11:28:10 +08:00
|
|
|
add_llvm_library(LLVMAMDGPUDesc
|
2012-12-12 05:25:42 +08:00
|
|
|
AMDGPUAsmBackend.cpp
|
2013-04-16 01:51:21 +08:00
|
|
|
AMDGPUELFObjectWriter.cpp
|
2015-09-26 05:41:28 +08:00
|
|
|
AMDGPUELFStreamer.cpp
|
2017-03-23 06:32:22 +08:00
|
|
|
AMDGPUMCAsmInfo.cpp
|
2013-11-19 08:57:56 +08:00
|
|
|
AMDGPUMCCodeEmitter.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
AMDGPUMCTargetDesc.cpp
|
2015-06-27 05:15:07 +08:00
|
|
|
AMDGPUTargetStreamer.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
R600MCCodeEmitter.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
R600MCTargetDesc.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
SIMCCodeEmitter.cpp
|
2017-03-23 06:32:22 +08:00
|
|
|
)
|
